View MB95F476HPMC2-G-SNE2_8928755.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mb95410h/470h series new 8fx 8-bit microcontrollers cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-07475 rev. *b revised august 24, 2017 mb95410h/470h is a series of general-purpose, single-chip micr ocontrollers. in addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral resources. features f 2 mc-8fx cpu core instruction set opti mized for controllers multiplication and division instructions 16-bit arithmetic operations bit test branch instructions bit manipulation instructions, etc. clock selectable main clock source ? main osc clock (up to 16.25 mhz, maximum machine clock frequency: 8.125 mhz) ? external clock (up to 32.5 mhz, maximum machine clock frequency: 16.25 mhz) ? main cr clock (1/8/10/12.5 mhz ? 2%, maximum machine clock frequency: 12.5 mhz) ? main pll clock (up to 16.25 mhz, maximum machine clock frequency: 16.25 mhz) selectable subclock source ? sub-osc clock (32.768 khz) ? external clock (32.768 khz) ? sub-cr clock (typ: 100 khz, min: 50 khz, max: 200 khz) timer 8/16-bit composite timer ? 2 channels 8/16-bit ppg ? 2 channels 16-bit reload timer ? 1 channel event counter ? 1 channel time-base timer ? 1 channel watch prescaler ? 1 channel uart-sio capable of clock-asynchronous (uart) serial data transfer and clock-synchronous (sio) serial data transfer full duplex double buffer i 2 c built-in wake-up function external interrupt interrupt by edge detection (rising edge, falling edge, and both edges can be selected) can be used to wake up the device from different low power consumption (standby) modes 8/10-bit a/d converter 8-bit or 10-bit resolution can be selected lcd controller (lcdc) on mb95f414h/f414k/f416h/f416k/f418h/f418k, lcd output can be selected from 40 seg ? 4 com to 36 seg ? 8 com. on mb95f474h/f474k/f476h/f476k/f478h/f478k, lcd output can be selected from 32 seg ? 4 com to 28 seg ? 8 com. internal divider resistor whos e resistance value can be selected from 10 k ? or 100 k ? through software interrupt in sync with the lcd module frame frequency blinking function inverted display function low power consumption (standby) modes stop mode sleep mode watch mode time-base timer mode i/o port mb95f414h/f416h/f418h (maximum no. of i/o ports: 74) ? general-purpose i/o ports (n-ch open drain) : 3 ? general-purpose i/o ports (cmos i/o) : 71 mb95f414k/f416k/f418k (maxim um no. of i/o ports: 75) ? general-purpose i/o ports (n-ch open drain) : 4 ? general-purpose i/o ports (cmos i/o) : 71 mb95f474h/f476h/f478h (maximum no. of i/o ports: 58) ? general-purpose i/o ports (n-ch open drain) : 3 ? general-purpose i/o ports (cmos i/o) : 55 mb95f474k/f476k/f478k (maxim um no. of i/o ports: 59) ? general-purpose i/o ports (n-ch open drain) : 4 ? general-purpose i/o ports (cmos i/o) : 55 on-chip debug 1-wire serial control serial writing supported (asynchronous mode) hardware/software watchdog timer built-in hardware watchdog timer built-in software watchdog timer
mb95410h/470h series document number: 002-07475 rev. *b page 2 of 85 low-voltage detection reset circuit built-in low-voltage detector clock supervisor counter built-in clock supervi sor counter function programmable port input voltage level cmos input level / hysteresis input level dual operation flash memory the program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simultane- ously. flash memory security function protects the content of the flash memory
mb95410h/470h series document number: 002-07475 rev. *b page 3 of 85 contents product line-up ................................................................ 4 oscillation stabilization wait time ................................. 8 packages and corresponding products ........................ 8 differences among products and notes on product selection ........................................................ 9 pin assignment .............................................................. 10 pin description (mb95410h series) .............................. 12 pin description (mb95470h series) .............................. 18 i/o circuit type ............................................................... 23 notes on device handling ............................................. 28 pin connection ............................................................... 28 block diagram (mb95410h series ) ................ ........... .... 30 block diagram (mb95470h series ) ................ ........... .... 31 cpu core ......................................................................... 32 i/o map (mb95410h series) ........................................... 33 i/o map (mb95470h series) ....... .............. .............. ........ 39 interrupt source table ................................................... 45 electrical characteristics ............................................... 46 absolute maximum ratings ... .................................... 46 recommended operating conditions ....................... 48 dc characteristics .................................................... 49 ac characteristics ..................................................... 53 a/d converter ............................................................ 67 flash memory program/erase characteristics .......... 71 sample characteristics .................................................. 72 mask options .................................................................. 78 ordering information ...................................................... 79 package dimension ........................................................ 80 major changes ................................................................ 83 document history ........................................................... 84
mb95410h/470h series document number: 002-07475 rev. *b page 4 of 85 1. product line-up mb95410h series (continued) part number package mb95f414h mb95f416h mb95f418h mb95f414k mb95f416k mb95f418k type flash memory product clock supervisor counter it supervises the main clock oscillation. program rom capacity 20 kbyte 36 kbyte 60 kbyte 20 kbyte 36 kbyte 60 kbyte ram capacity 496 bytes 1008 bytes 2032 bytes 496 bytes 1008 bytes 2032 bytes low-voltage detection reset no yes reset input dedicated selected through software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general-purpose i/o ? i/o ports (max) : 74 ? cmos i/o : 71 ? n-ch open drain : 3 ? i/o ports (max) : 75 ? cmos i/o : 71 ? n-ch open drain : 4 time-base timer interval time: 0.256 ms - 8. 3 s (external clock frequency = 4 mhz) hardware/software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be used as the source clock of the hardware watchdog timer. wild register it can be used to replace three bytes of data. i 2 c 1 channel ? master/slave sending and receiving ? bus error function and arbitration function ? detecting transmitting direction function ? start condition repeated generation and detection functions ? built-in wake-up function uart/sio 3 channels ? data transfer with uart/sio is enabled. ? it has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate generator and an error detection function. ? it uses the nrz type transfer format. ? lsb-first data transfer and msb-fi rst data transfer are available to use. ? clock-asynchronous (uart) serial data transfer and clock-synchronous (sio) serial data transfer is enabled. 8/10-bit a/d converter 8 channels 8-bit or 10-bit resolution can be selected.
mb95410h/470h series document number: 002-07475 rev. *b page 5 of 85 (continued) part number package mb95f414h mb95f416h mb95f418h mb95f414k mb95f416k mb95f418k 8/16-bit composite timer 2 channels ? each timer can be configured as an "8-bit timer ? 2 channels" or a "16-bit timer ? 1 channel". ? it has built-in timer function, pwc functi on, pwm function and input capture function. ? count clock: it can be selected from inte rnal clocks (seven types) and external clocks. ? it can output square wave. lcd controller (lcdc) ? com output: 4 or 8 (selectable) ? seg output: 36 or 40 (selectable) - if the number of co m outputs is 4, the maximum number of se g outputs is 40, and the maximum number of pixels that can be displayed 160 (4 ? 40). - if the number of com outputs is 8, the maximum nu mber of seg outputs is 36 , and the maximum number of pixels that can be displayed 288 (8 ? 36). ? lcd drive power supply (bias) pins: 5 (max) ? duty lcd mode ? lcd standby mode ? blinking function ? internal divider resistor whose resistance value can be selected from 10 k ? or 100 k ? through software ? interrupt in sync with the lcd module frame frequency ? inverted display function 16-bit reload timer 1 channel ? two clock modes and two counter operating modes can be selected ? square waveform output ? count clock: it can be selected from inte rnal clocks (seven types) and external clocks. ? counter operating mode: reload m ode or one-shot mode can be selected event counter by configuring the 16-bit reload timer and the 8/16-b it composite timer ch. 1, event counter function can be implemented. when the even t counter function is used, the 16-bit re load timer and the 8/16-bit composite timer ch. 1 are unavailable. 8/16-bit ppg 2 channels ? each channel of the ppg can be used as ?8-bit ppg ? 2 channels? or ?16-bit ppg ? 1 channel? ? counter operating clock: ei ght selectable clock sources watch counter ? count clock: four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s) ? counter value can be set from 0 to 63. (capable of c ounting for 1 minute when the clock source is 1 second and the counter value is to 60) external interrupt 8 channels ? interrupt by edge detection (the rising edge, falling edge, or both edges can be selected.) ? it can be used to wake up the device from the standby mode. on-chip debug ? 1-wire serial control ? it supports serial writing. (asynchronous mode) watch prescaler eight different time intervals can be selected. (62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s) flash memory ? it supports automatic programming, embedded algo rithm, program/erase/era se-suspend/erase-resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? number of program/erase cycles: 100000 ? data retention time: 20 years ? flash security feature for protec ting the content of the flash memory standby mode sleep mode, stop mode, watch mode, time-base timer mode package fpt-80p-m37
mb95410h/470h series document number: 002-07475 rev. *b page 6 of 85 mb95470h series (continued) part number package mb95f474h mb95f476h mb95f478h mb95f474k mb95f476k mb95f478k type flash memory product clock supervisor counter it supervises the main clock oscillation. program rom capacity 20 kbyte 36 kbyte 60 kbyte 20 kbyte 36 kbyte 60 kbyte ram capacity 496 bytes 1008 bytes 2032 bytes 496 bytes 1008 bytes 2032 bytes low-voltage detection reset no yes reset input dedicated selected through software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general-purpose i/o ? i/o ports (max) : 58 ? cmos i/o : 55 ? n-ch open drain : 3 ? i/o ports (max) : 59 ? cmos i/o : 55 ? n-ch open drain : 4 time-base timer interval time: 0.256 ms - 8.3 s (external clock frequency = 4 mhz) hardware/software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be used as the source clock of the hardware watchdog timer. wild register it can be used to replace three bytes of data. i 2 c 1 channel ? master/slave sending and receiving ? bus error function and arbitration function ? detecting transmitting direction function ? start condition repeated generation and detection functions ? built-in wa ke-up function uart/sio 3 channels ? data transfer with uart/sio is enabled. ? it has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate generator and an error detection function. ? it uses the nrz type transfer format. ? lsb-first data transfer and msb-first data transfer are available to use. ? clock-asynchronous (uart) serial data transfer and clock-synchronous (sio) serial data transfer is enabled. 8/10-bit a/d converter 8 channels 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 2 channels ? each timer can be configured as an "8-bit timer ? 2 channels" or a "16-bit timer ? 1 channel". ? it has built-in timer function, pwc functi on, pwm function and input capture function. ? count clock: it can be sele cted from internal clocks (sev en types) and external clocks. ? it can output square wave.
mb95410h/470h series document number: 002-07475 rev. *b page 7 of 85 (continued) part number package mb95f474h mb95f476h mb95f478h mb95f474k mb95f476k mb95f478k lcd controller (lcdc) ? com output: 4 or 8 (selectable) ? seg output: 28 or 32 (selectable) - if the number of com outputs is 4, the maximum number of seg outp uts is 32, and the maximum number of pixels that can be displayed 128 (4 ? 32). - if the number of com outputs is 8, the maximum number of seg outp uts is 28, and the maximum number of pixels that can be displayed 224 (8 ? 28). ? lcd drive power supply (bias) pins: 4 (max) ? duty lcd mode ? lcd standby mode ? blinking function ? internal divider resistor whose resi stance value can be selected from 10 k ? or 100 k ? through software ? inverted display function 16-bit reload timer 1 channel ? two clock modes and two counter operating modes can be selected ? square waveform output ? count clock: it can be sele cted from internal clocks (sev en types) and external clocks. ? counter operating mode: reload mode or one-shot mode can be selected event counter by configuring the 16-bit reload ti mer and the 8/16-bit composite timer ch. 1, event counter function can be implemented. when the event counter function is used, the 16-bit rel oad timer and the 8/16-bit composite timer ch. 1 are unavailable. 8/16-bit ppg 2 channels ? each channel of the ppg can be used as ?8-bit ppg ? 2 channels? or ?16-bit ppg ? 1 channel? ? counter operating clock: eight selectable clock sources watch counter ? count clock: four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s) ? counter value can be set from 0 to 63. (capable of counting for 1 minute when the clock source is 1 second and the counter value is to 60) external interrupt 8 channels interrupt by edge detection (the rising edge, falling edge, or both edges can be selected.) it can be used to wake up the device from the standby mode. on-chip debug ? 1-wire serial control ? it supports serial writing. (asynchronous mode) watch prescaler eight different time intervals can be selected. (62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s) flash memory ? it supports automatic programming, embedded algor ithm, program/erase/erase-suspend/erase-resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? number of program/erase cycles: 100000 ? data retention time: 20 years ? flash security feature for protec ting the content of the flash memory standby mode sleep mode, stop mode, watch mode, time-base timer mode package fpt-64p-m38 fpt-64p-m39
mb95410h/470h series document number: 002-07475 rev. *b page 8 of 85 2. oscillation stabilization wait time the main cr clock oscillation stabilization wait time is fixed to the maximum value. below is the maximum value. the main pll clock oscillation stabilization wait time is fixed to the maximum value. below is the maximum value. 3. packages and corresponding products o: available oscillation stabilization wait time remarks (2 10 ? 2) / f crh approx. 128 s (when the main cr clock is 8 mhz) oscillation stabilization wait time remarks (2 14 ? 2) / f ch approx. 14.1 ms (when the main pll clock is 4 mhz) part number package mb95f414h mb95f416h mb95f418h mb95f414k mb95f416k mb95f418k fpt-80p-m37 o part number package mb95f474h mb95f476h mb95f478h mb95f474k mb95f476k mb95f478k fpt-64p-m38 o fpt-64p-m39 o
mb95410h/470h series document number: 002-07475 rev. *b page 9 of 85 4. differences among products and not es on product selection current consumption when using the on-chip debug function, take account of the current consumption of flash erase/write. for details of current consumption, se e ?17. electrical characteristics?. package for details of information on each package, see ?3. package s and corresponding products? and ?21. package dimension?. operating voltage the operating voltage varies, depending on whether the on-chip debug function is used or not. for details of the operating voltage, s ee ?17. electrical characteristics?. on-chip debug function the on-chip debug functi on requires that v cc , v ss and 1 serial-wire be connected to an eval uation tool. for details of the connection method, refer to ?chapter 31 example of serial programming connection? in the hardware manual of the mb95410h/470h series.
mb95410h/470h series document number: 002-07475 rev. *b page 10 of 85 5. pin assignment (continued) p07/int07/an07/seg30 p06/int06/an06/seg31 p05/int05/an05/seg32/uck1 p04/int04/an04/seg33/ui1 p03/int03/an03/seg34/uo1 p02/int02/an02/seg35/uck2 p01/int01/an01/seg36/ui2 p00/int00/an00/uo2 p16/ppg10 p15/ppg11 p14/uck0 (top view) mb95410h series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 20 19 18 17 16 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 avcc p12/dbg p11/uo0 p10/ui0 p53/to0 p52/ti0/to00 p51/ec0 p50/to01 p13/adtg p22/scl p21/ppg01/cmpp p20/ppg00/cmpn p90/v4 p91/v3 p92/v2 p93/v1 p94/v0 pb2/seg37 pb3/seg38 pb4/seg39 p23/sda pa1/com1 pa2/com2 pa3/com3 pa4/com4 pa5/com5 pa6/com6 pa7/com7 pa0/com0 pc7/seg09 pc6/seg08 pc5/seg07 pc4/seg06 pc3/seg05 pc2/seg04 pc1/seg03 pc0/seg02 pb1/seg01 pb0/seg00 p17/cmpo 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 41 42 43 44 45 p60/seg10 vcc pg1/x0a pg2/x1a c pf0/x0 pf1/x1 vss pf2/rst pe7/seg29/ec1 pe6/seg28/to10 pe5/seg27/to11 pe4/seg26 pe3/seg25 pe2/seg24 pe1/seg23 pe0/seg22 p40/seg21 p41/seg20 p42/seg19 avss p67/seg17 p66/seg16 p65/seg15 p64/seg14 p63/seg13 p62/seg12 p61/seg11 p43/seg18 (fpt-80p-m37)
mb95410h/470h series document number: 002-07475 rev. *b page 11 of 85 (continued) p07/int07/an07/seg22 p06/int06/an06/seg23 p05/int05/an05/seg24/uck1 p04/int04/an04/seg25/ui1 p03/int03/an03/seg26/uo1 p02/int02/an02/seg27/uck2 p01/int01/an01/seg28/to00/ui2 p00/int00/an00/seg29/uo2 p16/seg30/ppg10 p15/seg31/ppg11 p14/uck0/ec0/ti0 (top view) mb95470h series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avcc p12/dbg p11/uo0 p10/ui0/to0 p13/adtg/to01 p22/scl p21/ppg01/cmpp p20/ppg00/cmpn p90/v4 p91/v3 p92/v2 p93/v1 p23/sda pa1/com1 pa2/com2 pa3/com3 pa4/com4 pa5/com5 pa6/com6 pa7/com7 pa0/com0 p60/seg06 pc3/seg05 pc2/seg04 pc1/seg03 pc0/seg02 pb1/seg01 pb0/seg00 p17/cmpo 48 47 46 45 44 43 42 41 40 39 38 33 34 35 36 37 vcc pg1/x0a pg2/x1a c pf0/x0 pf1/x1 vss pf2/rst pe7/seg21/ec1 pe6/seg20/to10 pe5/seg19/to11 pe4/seg18 pe3/seg17 pe2/seg16 pe1/seg15 pe0/seg14 avss p67/seg13 p66/seg12 p65/seg11 p64/seg10 p63/seg09 p62/seg08 p61/seg07 (fpt-64p-m38) (fpt-64p-m39)
mb95410h/470h series document number: 002-07475 rev. *b page 12 of 85 6. pin descript ion (mb95410h series) (continued) pin no. pin name i/o circuit type* function 1av cc ? a/d converter power supply pin 2 p07 s general-purpose i/o port int07 external interrupt input pin an07 a/d analog input pin seg30 lcdc seg output pin 3 p06 s general-purpose i/o port int06 external interrupt input pin an06 a/d analog input pin seg31 lcdc seg output pin 4 p05 s general-purpose i/o port int05 external interrupt input pin an05 a/d analog input pin seg32 lcdc seg output pin uck1 uart/sio ch. 1 clock i/o pin 5 p04 v general-purpose i/o port int04 external interrupt input pin an04 a/d analog input pin seg33 lcdc seg output pin ui1 uart/sio ch. 1 data input pin 6 p03 s general-purpose i/o port int03 external interrupt input pin an03 a/d analog input pin seg34 lcdc seg output pin uo1 uart/sio ch. 1 data output pin 7 p02 s general-purpose i/o port int02 external interrupt input pin an02 a/d analog input pin seg35 lcdc seg output pin uck2 uart/sio ch. 2 clock i/o pin 8 p01 v general-purpose i/o port int01 external interrupt input pin an01 a/d analog input pin seg36 lcdc seg output pin ui2 uart/sio ch. 2 data input pin
mb95410h/470h series document number: 002-07475 rev. *b page 13 of 85 (continued) pin no. pin name i/o circuit type* function 9 p00 w general-purpose i/o port int00 external interrupt input pin an00 a/d analog input pin uo2 uart/sio ch. 2 data output pin 10 p16 y general-purpose i/o port ppg10 8/16-bit ppg ch. 1 output pin 11 p15 y general-purpose i/o port ppg11 8/16-bit ppg ch. 1 output pin 12 p14 h general-purpose i/o port uck0 uart/sio ch. 0 clock i/o pin 13 p13 h general-purpose i/o port adtg a/d trigger input (adtg) pin 14 p12 d general-purpose i/o port dbg dbg input pin 15 p11 h general-purpose i/o port uo0 uart/sio ch. 0 data output pin 16 p10 g general-purpose i/o port ui0 uart/sio ch. 0 data input pin 17 p53 h general-purpose i/o port to0 16-bit reload timer output pin 18 p52 h general-purpose i/o port ti0 16-bit reload timer input pin to00 8/16-bit composite timer ch. 0 output pin 19 p51 h general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin 20 p50 h general-purpose i/o port to01 8/16-bit composite timer ch. 0 output pin 21 p23 i general-purpose i/o port sda i 2 c data i/o pin 22 p22 i general-purpose i/o port scl i 2 c clock i/o pin 23 p21 t general-purpose i/o port ppg01 8/16-bit ppg ch. 0 output pin cmpp voltage comparator input pin 24 p20 t general-purpose i/o port ppg00 8/16-bit ppg ch. 0 output pin cmpn voltage comparator input pin
mb95410h/470h series document number: 002-07475 rev. *b page 14 of 85 (continued) pin no. pin name i/o circuit type* function 25 p90 r general-purpose i/o port v4 lcdc drive power supply pin 26 p91 r general-purpose i/o port v3 lcdc drive power supply pin 27 p92 r general-purpose i/o port v2 lcdc drive power supply pin 28 p93 r general-purpose i/o port v1 lcdc drive power supply pin 29 p94 r general-purpose i/o port v0 lcdc drive power supply pin 30 pb2 m general-purpose i/o port seg37 lcdc seg output pin 31 pb3 m general-purpose i/o port seg38 lcdc seg output pin 32 pb4 m general-purpose i/o port seg39 lcdc seg output pin 33 pa0 m general-purpose i/o port com0 lcdc com output pin 34 pa1 m general-purpose i/o port com1 lcdc com output pin 35 pa2 m general-purpose i/o port com2 lcdc com output pin 36 pa3 m general-purpose i/o port com3 lcdc com output pin 37 pa4 m general-purpose i/o port com4 lcdc com output pin 38 pa5 m general-purpose i/o port com5 lcdc com output pin 39 pa6 m general-purpose i/o port com6 lcdc com output pin 40 pa7 m general-purpose i/o port com7 lcdc com output pin 41 v ss ? power supply pin (gnd) 42 pf1 b general-purpose i/o port x1 main clock oscillation pin 43 pf0 b general-purpose i/o port x0 main clock oscillation pin
mb95410h/470h series document number: 002-07475 rev. *b page 15 of 85 (continued) pin no. pin name i/o circuit type* function 44 c ? capacitor connection pin 45 pg2 c general-purpose i/o port x1a subclock oscillation pin (32 khz) 46 pg1 c general-purpose i/o port x0a subclock oscillation pin (32 khz) 47 v cc ? power supply pin 48 pf2 a general-purpose i/o port rst reset pin dedicate reset pin for mb95f414h/f416h/f418h 49 p17 h general-purpose i/o port cmpo voltage compar ator output pin 50 pb0 m general-purpose i/o port seg00 lcdc seg output pin 51 pb1 m general-purpose i/o port seg01 lcdc seg output pin 52 pc0 m general-purpose i/o port seg02 lcdc seg output pin 53 pc1 m general-purpose i/o port seg03 lcdc seg output pin 54 pc2 m general-purpose i/o port seg04 lcdc seg output pin 55 pc3 m general-purpose i/o port seg05 lcdc seg output pin 56 pc4 m general-purpose i/o port seg06 lcdc seg output pin 57 pc5 m general-purpose i/o port seg07 lcdc seg output pin 58 pc6 m general-purpose i/o port seg08 lcdc seg output pin 59 pc7 m general-purpose i/o port seg09 lcdc seg output pin 60 p60 m general-purpose i/o port seg10 lcdc seg output pin 61 p61 m general-purpose i/o port seg11 lcdc seg output pin 62 p62 m general-purpose i/o port seg12 lcdc seg output pin
mb95410h/470h series document number: 002-07475 rev. *b page 16 of 85 (continued) pin no. pin name i/o circuit type* function 63 p63 m general-purpose i/o port seg13 lcdc seg output pin 64 p64 m general-purpose i/o port seg14 lcdc seg output pin 65 p65 m general-purpose i/o port seg15 lcdc seg output pin 66 p66 m general-purpose i/o port seg16 lcdc seg output pin 67 p67 m general-purpose i/o port seg17 lcdc seg output pin 68 p43 m general-purpose i/o port seg18 lcdc seg output pin 69 p42 m general-purpose i/o port seg19 lcdc seg output pin 70 p41 m general-purpose i/o port seg20 lcdc seg output pin 71 p40 m general-purpose i/o port seg21 lcdc seg output pin 72 pe0 m general-purpose i/o port seg22 lcdc seg output pin 73 pe1 m general-purpose i/o port seg23 lcdc seg output pin 74 pe2 m general-purpose i/o port seg24 lcdc seg output pin 75 pe3 m general-purpose i/o port seg25 lcdc seg output pin 76 pe4 m general-purpose i/o port seg26 lcdc seg output pin 77 pe5 m general-purpose i/o port seg27 lcdc seg output pin to11 8/16-bit composite timer ch. 1 output pin 78 pe6 m general-purpose i/o port seg28 lcdc seg output pin to10 8/16-bit composite timer ch. 1 output pin
mb95410h/470h series document number: 002-07475 rev. *b page 17 of 85 (continued) *: for the i/o circuit types, see ?8. i/o circuit type?. pin no. pin name i/o circuit type* function 79 pe7 m general-purpose i/o port seg29 lcdc seg output pin ec1 8/16-bit composite timer ch. 1 clock input pin 80 av ss ? a/d converter power supply pin (gnd)
mb95410h/470h series document number: 002-07475 rev. *b page 18 of 85 7. pin descript ion (mb95470h series) (continued) pin no. pin name i/o circuit type* function 1av cc ? a/d converter power supply pin 2 p07 s general-purpose i/o port int07 external interrupt input pin an07 a/d analog input pin seg22 lcdc seg output pin 3 p06 s general-purpose i/o port int06 external interrupt input pin an06 a/d analog input pin seg23 lcdc seg output pin 4 p05 s general-purpose i/o port int05 external interrupt input pin an05 a/d analog input pin seg24 lcdc seg output pin uck1 uart/sio ch. 1 clock i/o pin 5 p04 v general-purpose i/o port int04 external interrupt input pin an04 a/d analog input pin seg25 lcdc seg output pin ui1 uart/sio ch. 1 data input pin 6 p03 s general-purpose i/o port int03 external interrupt input pin an03 a/d analog input pin seg26 lcdc seg output pin uo1 uart/sio ch. 1 data output pin 7 p02 s general-purpose i/o port int02 external interrupt input pin an02 a/d analog input pin seg27 lcdc seg output pin uck2 uart/sio ch. 2 clock i/o pin 8 p01 v general-purpose i/o port int01 external interrupt input pin an01 a/d analog input pin seg28 lcdc seg output pin to00 8/16-bit composite timer ch. 0 output pin ui2 uart/sio ch. 2 data input pin
mb95410h/470h series document number: 002-07475 rev. *b page 19 of 85 (continued) pin no. pin name i/o circuit type* function 9 p00 s general-purpose i/o port int00 external interrupt input pin an00 a/d analog input pin seg29 lcdc seg output pin uo2 uart/sio ch. 2 data output pin 10 p16 m general-purpose i/o port seg30 lcdc seg output pin ppg10 8/16-bit ppg ch. 1 output pin 11 p15 m general-purpose i/o port seg31 lcdc seg output pin ppg11 8/16-bit ppg ch. 1 output pin 12 p14 h general-purpose i/o port uck0 uart/sio ch. 0 clock i/o pin ec0 8/16-bit composite timer ch. 0 clock input pin ti0 16-bit reload timer input pin 13 p13 h general-purpose i/o port adtg a/d trigger input (adtg) pin to01 8/16-bit composite timer ch. 0 output pin 14 p12 d general-purpose i/o port dbg dbg input pin 15 p11 h general-purpose i/o port uo0 uart/sio ch. 0 data output pin 16 p10 g general-purpose i/o port ui0 uart/sio ch. 0 data input pin to0 16-bit reload timer output pin 17 p23 i general-purpose i/o port sda i 2 c data i/o pin 18 p22 i general-purpose i/o port scl i 2 c clock i/o pin 19 p21 t general-purpose i/o port ppg01 8/16-bit ppg ch. 0 output pin cmpp voltage comparator input pin 20 p20 t general-purpose i/o port ppg00 8/16-bit ppg ch. 0 output pin cmpn voltage comparator input pin
mb95410h/470h series document number: 002-07475 rev. *b page 20 of 85 (continued) pin no. pin name i/o circuit type* function 21 p90 r general-purpose i/o port v4 lcdc drive power supply pin 22 p91 r general-purpose i/o port v3 lcdc drive power supply pin 23 p92 r general-purpose i/o port v2 lcdc drive power supply pin 24 p93 r general-purpose i/o port v1 lcdc drive power supply pin 25 pa0 m general-purpose i/o port com0 lcdc com output pin 26 pa1 m general-purpose i/o port com1 lcdc com output pin 27 pa2 m general-purpose i/o port com2 lcdc com output pin 28 pa3 m general-purpose i/o port com3 lcdc com output pin 29 pa4 m general-purpose i/o port com4 lcdc com output pin 30 pa5 m general-purpose i/o port com5 lcdc com output pin 31 pa6 m general-purpose i/o port com6 lcdc com output pin 32 pa7 m general-purpose i/o port com7 lcdc com output pin 33 v ss ? power supply pin (gnd) 34 pf1 b general-purpose i/o port x1 main clock oscillation pin 35 pf0 b general-purpose i/o port x0 main clock oscillation pin 36 c ? capacitor connection pin 37 pg2 c general-purpose i/o port x1a subclock oscillation pin (32 khz) 38 pg1 c general-purpose i/o port x0a subclock oscillation pin (32 khz) 39 v cc ? power supply pin 40 pf2 a general-purpose i/o port rst reset pin dedicated reset pin for mb95f474h/f476h/f478h
mb95410h/470h series document number: 002-07475 rev. *b page 21 of 85 (continued) pin no. pin name i/o circuit type* function 41 p17 h general-purpose i/o port cmpo voltage compar ator output pin 42 pb0 m general-purpose i/o port seg00 lcdc seg output pin 43 pb1 m general-purpose i/o port seg01 lcdc seg output pin 44 pc0 m general-purpose i/o port seg02 lcdc seg output pin 45 pc1 m general-purpose i/o port seg03 lcdc seg output pin 46 pc2 m general-purpose i/o port seg04 lcdc seg output pin 47 pc3 m general-purpose i/o port seg05 lcdc seg output pin 48 p60 m general-purpose i/o port seg06 lcdc seg output pin 49 p61 m general-purpose i/o port seg07 lcdc seg output pin 50 p62 m general-purpose i/o port seg08 lcdc seg output pin 51 p63 m general-purpose i/o port seg09 lcdc seg output pin 52 p64 m general-purpose i/o port seg10 lcdc seg output pin 53 p65 m general-purpose i/o port seg11 lcdc seg output pin 54 p66 m general-purpose i/o port seg12 lcdc seg output pin 55 p67 m general-purpose i/o port seg13 lcdc seg output pin 56 pe0 m general-purpose i/o port seg14 lcdc seg output pin 57 pe1 m general-purpose i/o port seg15 lcdc seg output pin
mb95410h/470h series document number: 002-07475 rev. *b page 22 of 85 (continued) *: for the i/o circuit types, see ?8. i/o circuit type?. pin no. pin name i/o circuit type* function 58 pe2 m general-purpose i/o port seg16 lcdc seg output pin 59 pe3 m general-purpose i/o port seg17 lcdc seg output pin 60 pe4 m general-purpose i/o port seg18 lcdc seg output pin 61 pe5 m general-purpose i/o port seg19 lcdc seg output pin to11 8/16-bit composite timer ch. 1 output pin 62 pe6 m general-purpose i/o port seg20 lcdc seg output pin to10 8/16-bit composite timer ch. 1 output pin 63 pe7 m general-purpose i/o port seg21 lcdc seg output pin ec1 8/16-bit composite timer ch. 1 clock input pin 64 av ss ? a/d converter power supply pin (gnd)
mb95410h/470h series document number: 002-07475 rev. *b page 23 of 85 8. i/o circuit type (continued) type circuit remarks a ? n-ch open drain output ? hysteresis input ? reset output b ? oscillation circuit ? high-speed side feedback resistance: approx. 1 m ? ? cmos output ? hysteresis input c ? oscillation circuit ? low-speed side feedback resistance: approx. 10 m ? ? cmos output ? hysteresis input ? pull-up control available n-ch reset output / digital output reset input / hysteresis input standby control / port select clock input port select digital output digital output standby control hysteresis input digital output digital output standby control hysteresis input port select x1 x0 n-ch p-ch n-ch p-ch clock input x1a x0a standby control / port select n-ch p-ch port select digital output digital output standby control hysteresis input n-ch digital output digital output digital output standby control hysteresis input p-ch r pull-up control port select p-ch r pull-up control
mb95410h/470h series document number: 002-07475 rev. *b page 24 of 85 (continued) type circuit remarks d ? n-ch open drain output ? hysteresis input g ? cmos output ? hysteresis input ?cmos input ? pull-up control available h ? cmos output ? hysteresis input ? pull-up control available i ? n-ch open drain output ?cmos input ? hysteresis input j ? cmos output ? hysteresis input ? analog input ? pull-up control available n-ch standby control hysteresis input digital output n-ch p-ch p-ch r pull-up control digital output digital output standby control hysteresis input cmos input n-ch p-ch p-ch r pull-up control digital output digital output standby control hysteresis input n-ch standby control hysteresis input digital output cmos input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control standby control hysteresis input
mb95410h/470h series document number: 002-07475 rev. *b page 25 of 85 (continued) type circuit remarks m ?cmos output ? lcd output ? hysteresis input n ?cmos output ? lcd output ? hysteresis input ? cmos input q ?cmos output ? lcd output ? hysteresis input r ?cmos output ? lcd power supply ? hysteresis input n-ch p-ch digital output digital output lcd output lcd control standby control hysteresis input n-ch p-ch digital output digital output lcd output lcd control standby control hysteresis input cmos input n-ch p-ch digital output digital output lcd output lcd control hysteresis input standby control external interrupt control n-ch p-ch digital output digital output lcd control standby control hysteresis input lcd internal divider resistor i/o
mb95410h/470h series document number: 002-07475 rev. *b page 26 of 85 (continued) type circuit remarks s ?cmos output ? lcd output ? hysteresis input ? analog input t ?cmos output ? hysteresis input ? analog input ? pull-up control available v ?cmos output ? lcd output ? hysteresis input ? analog input ? cmos input n-ch p-ch digital output digital output analog input lcd output lcd control a/d control standby control hysteresis input n-ch p-ch r pull-up control digital output digital output analog input analog input control standby control hysteresis input n-ch p-ch digital output digital output analog input lcd output lcd control a/d control standby control hysteresis input cmos input
mb95410h/470h series document number: 002-07475 rev. *b page 27 of 85 (continued) type circuit remarks w ?cmos output ? hysteresis input ? analog input y ?cmos output ? hysteresis input n-ch p-ch digital output digital output analog input analog input control standby control hysteresis input n-ch p-ch digital output digital output standby control hysteresis input
mb95410h/470h series document number: 002-07475 rev. *b page 28 of 85 9. notes on device handling preventing latch-ups when using the device, ensure that the voltage a pplied does not exceed the maximum voltage rating. in a cmos ic, if a voltage higher than v cc or a voltage lower than v ss is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withs tand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in "17.1 absolute maximum ratings" of ?17. el ectrical characteristics? is applied to the v cc pin or the v ss pin, a latch-up may occur. when a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. stabilizing supply voltage supply voltage must be stabilized. a malfunction may occur when power supply voltage fluctuates ra pidly even though the fluctuation is within the guaranteed opera ting range of the v cc power supply voltage. as a rule of voltage stabilization, suppress volt age fluctuation so that the fluctuation in v cc ripple (p-p value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard v cc value, and the transient fluctuation rate does not exceed 0.1 v/ms at a momentary fluctuation such as switching the power supply. notes on using the external clock when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. 10. pin connection treatment of unused input pins if an unused input pin is left unconnected, a component may be pe rmanently damaged due to malfunctions or latch-ups. always pul l up or pull down an unused input pin through a resistor of at least 2 k ? . set an unused input/output pin to the output state and leave it unconnected, or set it to the input stat e and treat it the same as an unused input pin. if there is an unused output pin, le ave it unconnected. power supply pins to reduce unnecessary electro-magnetic emissi on, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the v cc pin and the v ss pin to the power supply and ground outside the device. in addition, connect the current supply source to the v cc pin and the v ss pin with low impedance. it is also advisable to connect a ceramic capacitor of a pproximately 0.1 f as a bypass capacitor between the v cc pin and the v ss pin at a location close to this device. dbg pin connect the dbg pin directly to an external pull-up resistor. to prevent the device from unintentionally entering the debug mode due to noise, minimize the di stance between the dbg pin and the v cc or v ss pin when designing the layout of the printed circuit board. the dbg pin should not stay at ?l? level afte r power-on until the reset output is released. rst pin connect the rst pin directly to an external pull-up resistor. to prevent the device from unintentionally entering the rese t mode due to noise, minimi ze the distance between the rst pin and the v cc or v ss pin when designing the layout of the printed circuit board. the pf2/rst pin functions as the reset input/output pin after power-on. in addition, the reset output function of the pf2/rst pin can be enabled by the rstoe bit in the sysc register, and the reset i nput function or the general purpose i/o function can be selec ted by the rsten bit in the sysc register. analog power supply always set the same potential to av cc and v cc pins. when v cc is larger than av cc , the current may flow through the an00 to an07 pins.
mb95410h/470h series document number: 002-07475 rev. *b page 29 of 85 treatment of power supply pins on the a/d converter ensure that av cc is equal to v cc and av ss equal to v ss even when the a/d converter is not in use. noise riding on the av cc pin may cause accuracy degradation. therefore, connec t a ceramic capacitor of 0.1 f (approx.) as a bypass capacitor between the av cc pin and the av ss pin in the vicinity of this device. c pin use a ceramic capacitor or a capacitor with equivalent fr equency characteristics. t he bypass capacitor for the v cc pin must have a capacitance larger than c s . for the connection to a smoothing capacitor c s , see the diagram below. to prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. c cs dbg rst dbg/rst /c pins connection diagram
mb95410h/470h series document number: 002-07475 rev. *b page 30 of 85 11. block diagram (mb95410h series) reset with lvd flash with security function (60/36/20 kbyte) f 2 mc-8fx cpu ram (2032/1008/496 bytes) interrupt controller oscillator circuit cr oscillator clock control on-chip debug wild register watch counter external interrupt uart/sio ch. 0 8/16-bit composite timer ch. 0 8/10-bit a/d converter 16-bit reload timer 8/16-bit composite timer ch. 1 uart/sio ch. 1 i 2 c 8/16-bit ppg ch. 0 8/16-bit ppg ch. 1 port port pf2 *1 /rst *2 pf1/x1 *2 pf0/x0 *2 pg2/x1a *2 pg1/x0a *2 p00/int00 to p07/int07 c p14/uck0 p11/uo0 p10/ui0 p05/uck1 p03/uo1 p04/ui1 uart/sio ch. 2 p02/uck2 p00/uo2 p01/ui2 p20/ppg00 p21/ppg01 p16/ppg10 p15/ppg11 p22/scl *1 p23/sda *1 p12 *1 /dbg p52/to00 p50/to01 p51/ec0 p00/an00 to p07/an07 p13/adtg lcdc (4 com or 8 com) p90/v4 to p94/v0 pa0/com0 to pa3/com3 pb0/seg00, pb1/seg01 pc0/seg02 to pc7/seg09 p60/seg10 to p67/seg17 p43/seg18 to p40/seg21 pe0/seg22 to pe7/seg29 p07/seg30 to p01/seg36 pb2/seg37 to pb4/seg39 p90/v4 to p94/v0 4 com: 8 com: pa0/com0 to pa7/com7 pb0/seg00, pb1/seg01 pc0/seg02 to pc7/seg09 p60/seg10 to p67/seg17 p43/seg18 to p40/seg21 pe0/seg22 to pe7/seg29 p07/seg30 to p02/seg35 pe5/to11 pe6/to10 pe7/ec1 voltage comparator p20/cmpn p21/cmpp p17/cmpo p52/ti0 p53/to0 vcc vss *1: *2: *3: pf2, p12, p22 and p23 are n-ch open drain pins. software option 8/16-bit composite timer ch. 1 and 16-bit reload timer can be used as an event counter when the event counter operating mode is enabled. internal bus *3
mb95410h/470h series document number: 002-07475 rev. *b page 31 of 85 12. block diagram (mb95470h series) reset with lvd flash with security function (60/36/20 kbyte) f 2 mc-8fx cpu ram (2032/1008/496 bytes) interrupt controller oscillator circuit cr oscillator clock control on-chip debug wild register watch counter external interrupt uart/sio ch. 0 8/16-bit composite timer ch. 0 8/10-bit a/d converter 16-bit reload timer 8/16-bit composite timer ch. 1 uart/sio ch. 1 i 2 c 8/16-bit ppg ch. 0 8/16-bit ppg ch. 1 port port pf2 *1 /rst *2 pf1/x1 *2 pf0/x0 *2 pg2/x1a *2 pg1/x0a *2 p00/int00 to p07/int07 c p14/uck0 p11/uo0 p10/ui0 p05/uck1 p03/uo1 p04/ui1 uart/sio ch. 2 p02/uck2 p00/uo2 p01/ui2 p20/ppg00 p21/ppg01 p16/ppg10 p15/ppg11 p22 *1 /scl p23 *1 /sda p12 *1 /dbg p01/to00 p13/to01 p14/ec0 p00/an00 to p07/an07 p13/adtg lcdc (4 com or 8 com) p90/v4 to p93/v1 pa0/com0 to pa3/com3 pb0/seg00, pb1/seg01 pc0/seg02 to pc3/seg05 p60/seg06 to p67/seg13 pe0/seg14 to pe7/seg21 p07/seg22 to p00/seg29 p16/seg30, p15/seg31 p90/v4 to p93/v1 4 com: 8 com: pa0/com0 to pa7/com7 pb0/seg00, pb1/seg01 pc0/seg02 to pc3/seg05 p60/seg06 to p67/seg13 pe0/seg14 to pe7/seg21 p07/seg22 to p02/seg27 pe5/to11 pe6/to10 pe7/ec1 voltage comparator p20/cmpn p21/cmpp p17/cmpo p14/ti0 p10/to0 vcc vss *1: *2: *3: pf2, p12, p22 and p23 are n-ch open drain pins. software option 8/16-bit composite timer ch. 1 and 16-bit reload timer can be used as an event counter when the event counter operating mode is enabled. internal bus *3
mb95410h/470h series document number: 002-07475 rev. *b page 32 of 85 13. cpu core memory space the memory space of the mb95410h/470h series is 64 kbyte in size , and consists of an i/o area, a data area, and a program area. the memory space includes areas intended for specific purposes su ch as general-purpose registers and a vector table. the memory maps of the mb95410h/470h series are shown below. memory maps i/o area access prohibited ram 496 bytes registers access prohibited extended i/o area vacant flash 16 kbyte 0000 h 0080 h 0090 h 0100 h 0280 h 0200 h 0f80 h 1000 h 2000 h bfff h ffff h mb95f414h/f414k mb95f474h/f474k flash 4 kbyte i/o area access prohibited ram 1008 bytes registers access prohibited extended i/o area vacant flash 32 kbyte flash 4 kbyte 0000 h 0080 h 0090 h 0100 h 0200 h 0480 h 0f80 h 1000 h 2000 h 7fff h ffff h mb95f416h/f416k mb95f476h/f476k i/o area access prohibited ram 2032 bytes registers access prohibited extended i/o area flash 60 kbyte 0000 h 0080 h 0090 h 0100 h 0200 h 0880 h 0f80 h 1000 h ffff h mb95f418h/f418k mb95f478h/f478k
mb95410h/470h series document number: 002-07475 rev. *b page 33 of 85 14. i/o map (mb95410h series) (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h pllc pll control register r/w 00000000 b 0007 h sycc system clock control register r/w xxxxxx11 b 0008 h stbc standby control register r/w 00000xxx b 0009 h rsrr reset source register r/w 000xxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h sycc2 system clock control register 2 r/w xx100011 b 000e h pdr2 port 2 data register r/w 00000000 b 000f h ddr2 port 2 direction register r/w 00000000 b 0010 h , 0011 h ? (disabled) ? ? 0012 h pdr4 port 4 data register r/w 00000000 b 0013 h ddr4 port 4 direction register r/w 00000000 b 0014 h pdr5 port 5 data register r/w 00000000 b 0015 h ddr5 port 5 direction register r/w 00000000 b 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h to 001b h ? (disabled) ? ? 001c h pdr9 port 9 data register r/w 00000000 b 001d h ddr9 port 9 direction register r/w 00000000 b 001e h pdra port a data register r/w 00000000 b 001f h ddra port a direction register r/w 00000000 b 0020 h pdrb port b data register r/w 00000000 b 0021 h ddrb port b direction register r/w 00000000 b 0022 h pdrc port c data register r/w 00000000 b 0023 h ddrc port c direction register r/w 00000000 b 0024 h , 0025 h ? (disabled) ? ?
mb95410h/470h series document number: 002-07475 rev. *b page 34 of 85 (continued) address register abbreviation register name r/w initial value 0026 h pdre port e data register r/w 00000000 b 0027 h ddre port e direction register r/w 00000000 b 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h ? (disabled) ? ? 002d h pul1 port 1 pull-up register r/w 00000000 b 002e h pul2 port 2 pull-up register r/w 00000000 b 002f h , 0030 h ? (disabled) ? ? 0031 h pul5 port 5 pull-up register r/w 00000000 b 0032 h to 0034 h ? (disabled) ? ? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 r/w 00000000 b 0038 h t11cr1 8/16-bit composite timer 11 status control register 1 r/w 00000000 b 0039 h t10cr1 8/16-bit composite timer 10 status control register 1 r/w 00000000 b 003a h pc01 8/16-bit ppg01 control register r/w 00000000 b 003b h pc00 8/16-bit ppg00 control register r/w 00000000 b 003c h pc11 8/16-bit ppg11 control register r/w 00000000 b 003d h pc10 8/16-bit ppg10 control register r/w 00000000 b 003e h tmcsrh0 16-bit reload timer control status register upper r/w 00000000 b 003f h tmcsrl0 16-bit reload timer control status register lower r/w 00000000 b 0040 h to 0047 h ? (disabled) ? ? 0048 h eic00 external interrupt circuit cont rol register ch. 0/ch. 1 r/w 00000000 b 0049 h eic10 external interrupt circuit cont rol register ch. 2/ch. 3 r/w 00000000 b 004a h eic20 external interrupt circuit cont rol register ch. 4/ch. 5 r/w 00000000 b 004b h eic30 external interrupt circuit cont rol register ch. 6/ch. 7 r/w 00000000 b 004c h to 004e h ? (disabled) ? ? 004f h lcdcc2 lcdc control register 2 r/w 00010100 b 0050 h cmr0 voltage comparator control register r/w 000x0001 b 0051 h to 0055 h ? (disabled) ? ?
mb95410h/470h series document number: 002-07475 rev. *b page 35 of 85 (continued) address register abbreviation register name r/w initial value 0056 h smc10 uart/sio serial mode control register 1 ch. 0 r/w 00000000 b 0057 h smc20 uart/sio serial mode control register 2 ch. 0 r/w 00100000 b 0058 h ssr0 uart/sio serial status register ch. 0 r/w 00000001 b 0059 h tdr0 uart/sio serial output data register ch. 0 r/w 00000000 b 005a h rdr0 uart/sio serial input data register ch. 0 r 00000000 b 005b h smc11 uart/sio serial mode control register 1 ch. 1 r/w 00000000 b 005c h smc21 uart/sio serial mode control register 2 ch. 1 r/w 00100000 b 005d h ssr1 uart/sio serial status register ch. 1 r/w 00000001 b 005e h tdr1 uart/sio serial output data register ch. 1 r/w 00000000 b 005f h rdr1 uart/sio serial input data register ch. 1 r 00000000 b 0060 h ibcr00 i 2 c bus control register 0 r/w 00000001 b 0061 h ibcr10 i 2 c bus control register 1 r/w 00000000 b 0062 h ibcr0 i 2 c bus status register r 00000000 b 0063 h iddr0 i 2 c data register r/w 00000000 b 0064 h iaar0 i 2 c address register r/w 00000000 b 0065 h iccr0 i 2 c clock control register r/w 00000000 b 0066 h smc12 uart/sio serial mode control register 1 ch. 2 r/w 00000000 b 0067 h smc22 uart/sio serial mode control register 2 ch. 2 r/w 00100000 b 0068 h ssr2 uart/sio serial status register ch. 2 r/w 00000001 b 0069 h tdr2 uart/sio serial output data register ch. 2 r/w 00000000 b 006a h rdr2 uart/sio serial input data register ch. 2 r 00000000 b 006b h ? (disabled) ? ? 006c h adc1 8/10-bit a/d converter c ontrol register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter c ontrol register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter dat a register upper r/w 00000000 b 006f h addl 8/10-bit a/d converter data register lower r/w 00000000 b 0070 h wcsr watch counter stat us register r/w 00000000 b 0071 h fsr2 flash memory status register 2 r/w 00000000 b 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector writ e control register 0 r/w 00000000 b 0074 h fsr3 flash memory status register 3 r 00000000 b 0075 h ? (disabled) ? ? 0076 h wren wild register address co mpare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ? ?
mb95410h/470h series document number: 002-07475 rev. *b page 36 of 85 (continued) address register abbreviation register name r/w initial value 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ? ? 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch. 0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch. 2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 status control register 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 status control register 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 ti mer mode control register r/w 00000000 b 0f97 h t11cr0 8/16-bit composite timer 11 status control register 0 r/w 00000000 b 0f98 h t10cr0 8/16-bit composite timer 10 status control register 0 r/w 00000000 b 0f99 h t11dr 8/16-bit composite timer 11 data register r/w 00000000 b 0f9a h t10dr 8/16-bit composite timer 10 data register r/w 00000000 b 0f9b h tmcr1 8/16-bit composite timer 10/11 ti mer mode control register r/w 00000000 b 0f9c h pps01 8/16-bit ppg01 cycle setting buffer register r/w 11111111 b 0f9d h pps00 8/16-bit ppg00 cycle setting buffer register r/w 11111111 b 0f9e h pds01 8/16-bit ppg01 duty setting buffer register r/w 11111111 b 0f9f h pds00 8/16-bit ppg00 duty setting buffer register r/w 11111111 b 0fa0 h pps11 8/16-bit ppg11 cycle setting buffer register r/w 11111111 b 0fa1 h pps10 8/16-bit ppg10 cycle setting buffer register r/w 11111111 b 0fa2 h pds11 8/16-bit ppg11 duty setting buffer register r/w 11111111 b 0fa3 h pds10 8/16-bit ppg10 duty setting buffer register r/w 11111111 b
mb95410h/470h series document number: 002-07475 rev. *b page 37 of 85 (continued) address register abbreviation register name r/w initial value 0fa4 h ppgs 8/16-bit ppg start register r/w 00000000 b 0fa5 h revc 8/16-bit ppg output inversion register r/w 00000000 b 0fa6 h tmrh0 16-bit reload timer timer register upper r/w 00000000 b tmrlrh0 16-bit reload timer reload register upper r/w 00000000 b 0fa7 h tmrl0 16-bit reload timer timer register lower r/w 00000000 b tmrlrl0 16-bit reload timer reload register lower r/w 00000000 b 0fa8 h pssr0 uart/sio dedicated baud ra te generator prescaler sele ct register ch. 0 r/w 00000000 b 0fa9 h brsr0 uart/sio dedicated baud rate generator baud rate setting register ch. 0 r/w 00000000 b 0faa h pssr1 uart/sio dedicated baud ra te generator prescaler sele ct register ch. 1 r/w 00000000 b 0fab h brsr1 uart/sio dedicated baud rate generator baud rate setting register ch. 1 r/w 00000000 b 0fac h pssr2 uart/sio dedicated baud ra te generator prescaler sele ct register ch. 2 r/w 00000000 b 0fad h brsr2 uart/sio dedicated baud rate generator baud rate setting register ch. 2 r/w 00000000 b 0fae h ? (disabled) ? ? 0faf h aidrl a/d input disable register (lower) r/w 00000000 b 0fb0 h lcdcc1 lcdc control register 1 r/w 00000000 b 0fb1 h ? (disabled) ? ? 0fb2 h lcdce1 lcdc enable register 1 r/w 00111110 b 0fb3 h lcdce2 lcdc enable register 2 r/w 00000000 b 0fb4 h lcdce3 lcdc enable register 3 r/w 00000000 b 0fb5 h lcdce4 lcdc enable register 4 r/w 00000000 b 0fb6 h lcdce5 lcdc enable register 5 r/w 00000000 b 0fb7 h lcdce6 lcdc enable register 6 r/w 00000000 b 0fb8 h lcdce7 lcdc enable register 7 r/w 00000000 b 0fb9 h lcdcb1 lcdc blinking setting register 1 r/w 00000000 b 0fba h lcdcb2 lcdc blinking setting register 2 r/w 00000000 b 0fbb h , 0fbc h ? (disabled) ? ? 0fbd h to 0fe0 h lcdram lcdc display ram (36 bytes) r/w 00000000 b 0fe1 h ? (disabled) ? ? 0fe2 h evcr event counter control register r/w 00000000 b 0fe3 h wcdr watch counter data register r/w 00111111 b
mb95410h/470h series document number: 002-07475 rev. *b page 38 of 85 (continued) r/w access symbols initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. address register abbreviation register name r/w initial value 0fe4 h crth main cr clock trimming register (upper) r/w 0xxxxxxx b 0fe5 h crtl main cr clock trimming register (lower) r/w 00xxxxxx b 0fe6 h , 0fe7 h ? (disabled) ? ? 0fe8 h sysc system configurati on register r/w 11000011 b 0fe9 h cmcr clock monitoring control register r/w xx000000 b 0fea h cmdr clock monitoring data register r 00000000 b 0feb h wdth watchdog timer selection id register (upper) r xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r xxxxxxxx b 0fed h ? (disabled) ? ? 0fee h ilsr input level select register r/w 00000000 b 0fef h wicr interrupt pin control register r/w 01000000 b 0ff0 h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of th is bit is in determinate.
mb95410h/470h series document number: 002-07475 rev. *b page 39 of 85 15. i/o map (mb95470h series) (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h pllc pll control register r/w 00000000 b 0007 h sycc system clock control register r/w xxxxxx11 b 0008 h stbc standby control register r/w 00000xxx b 0009 h rsrr reset source register r/w 000xxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h sycc2 system clock control register 2 r/w xx100011 b 000e h pdr2 port 2 data register r/w 00000000 b 000f h ddr2 port 2 direction register r/w 00000000 b 0010 h to 0015 h ? (disabled) ? ? 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h to 001b h ? (disabled) ? ? 001c h pdr9 port 9 data register r/w 00000000 b 001d h ddr9 port 9 direction register r/w 00000000 b 001e h pdra port a data register r/w 00000000 b 001f h ddra port a direction register r/w 00000000 b 0020 h pdrb port b data register r/w 00000000 b 0021 h ddrb port b direction register r/w 00000000 b 0022 h pdrc port c data register r/w 00000000 b 0023 h ddrc port c direction register r/w 00000000 b 0024 h , 0025 h ? (disabled) ? ? 0026 h pdre port e data register r/w 00000000 b 0027 h ddre port e direction register r/w 00000000 b 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h ? (disabled) ? ?
mb95410h/470h series document number: 002-07475 rev. *b page 40 of 85 (continued) address register abbreviation register name r/w initial value 002d h pul1 port 1 pull-up register r/w 00000000 b 002e h pul2 port 2 pull-up register r/w 00000000 b 002f h to 0034 h ? (disabled) ? ? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 r/w 00000000 b 0038 h t11cr1 8/16-bit composite timer 11 status control register 1 r/w 00000000 b 0039 h t10cr1 8/16-bit composite timer 10 status control register 1 r/w 00000000 b 003a h pc01 8/16-bit ppg01 control register r/w 00000000 b 003b h pc00 8/16-bit ppg00 control register r/w 00000000 b 003c h pc11 8/16-bit ppg11 control register r/w 00000000 b 003d h pc10 8/16-bit ppg10 control register r/w 00000000 b 003e h tmcsrh0 16-bit reload timer control status register upper r/w 00000000 b 003f h tmcsrl0 16-bit reload timer control status register lower r/w 00000000 b 0040 h to 0047 h ? (disabled) ? ? 0048 h eic00 external interrupt circuit cont rol register ch. 0/ch. 1 r/w 00000000 b 0049 h eic10 external interrupt circuit cont rol register ch. 2/ch. 3 r/w 00000000 b 004a h eic20 external interrupt circuit cont rol register ch. 4/ch. 5 r/w 00000000 b 004b h eic30 external interrupt circuit cont rol register ch. 6/ch. 7 r/w 00000000 b 004c h to 004e h ? (disabled) ? ? 004f h lcdcc2 lcdc control register 2 r/w 00010100 b 0050 h cmr0 voltage comparator control register r/w 000x0001 b 0051 h to 0055 h ? (disabled) ? ? 0056 h smc10 uart/sio serial mode control register 1 ch. 0 r/w 00000000 b 0057 h smc20 uart/sio serial mode control register 2 ch. 0 r/w 00100000 b 0058 h ssr0 uart/sio serial status register ch. 0 r/w 00000001 b 0059 h tdr0 uart/sio serial output data register ch. 0 r/w 00000000 b 005a h rdr0 uart/sio serial input data register ch. 0 r 00000000 b 005b h smc11 uart/sio serial mode control register 1 ch. 1 r/w 00000000 b 005c h smc21 uart/sio serial mode control register 2 ch. 1 r/w 00100000 b 005d h ssr1 uart/sio serial status register ch. 1 r/w 00000001 b 005e h tdr1 uart/sio serial output data register ch. 1 r/w 00000000 b
mb95410h/470h series document number: 002-07475 rev. *b page 41 of 85 (continued) address register abbreviation register name r/w initial value 005f h rdr1 uart/sio serial input data register ch. 1 r 00000000 b 0060 h ibcr00 i 2 c bus control register 0 r/w 00000001 b 0061 h ibcr10 i 2 c bus control register 1 r/w 00000000 b 0062 h ibcr0 i 2 c bus status register r 00000000 b 0063 h iddr0 i 2 c data register r/w 00000000 b 0064 h iaar0 i 2 c address register r/w 00000000 b 0065 h iccr0 i 2 c clock control register r/w 00000000 b 0066 h smc12 uart/sio serial mode control register 1 ch. 2 r/w 00000000 b 0067 h smc22 uart/sio serial mode control register 2 ch. 2 r/w 00100000 b 0068 h ssr2 uart/sio serial status register ch. 2 r/w 00000001 b 0069 h tdr2 uart/sio serial output data register ch. 2 r/w 00000000 b 006a h rdr2 uart/sio serial input data register ch. 2 r 00000000 b 006b h ? (disabled) ? ? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register upper r/w 00000000 b 006f h addl 8/10-bit a/d converter data register lower r/w 00000000 b 0070 h wcsr watch counter status register r/w 00000000 b 0071 h fsr2 flash memory status register 2 r/w 00000000 b 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector writ e control register 0 r/w 00000000 b 0074 h fsr3 flash memory status register 3 r 00000000 b 0075 h ? (disabled) ? ? 0076 h wren wild register address co mpare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ? ? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ? ? 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data sett ing register ch. 0 r/w 00000000 b
mb95410h/470h series document number: 002-07475 rev. *b page 42 of 85 (continued) address register abbreviation register name r/w initial value 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data sett ing register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data sett ing register ch. 2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 status control register 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 status control register 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite time r 01 data register r/w 00000000 b 0f95 h t00dr 8/16-bit composite time r 00 data register r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 ti mer mode control register r/w 00000000 b 0f97 h t11cr0 8/16-bit composite timer 11 status control register 0 r/w 00000000 b 0f98 h t10cr0 8/16-bit composite timer 10 status control register 0 r/w 00000000 b 0f99 h t11dr 8/16-bit composite time r 11 data register r/w 00000000 b 0f9a h t10dr 8/16-bit composite time r 10 data register r/w 00000000 b 0f9b h tmcr1 8/16-bit composite timer 10/11 ti mer mode control register r/w 00000000 b 0f9c h pps01 8/16-bit ppg01 cycle setting buffer register r/w 11111111 b 0f9d h pps00 8/16-bit ppg00 cycle setting buffer register r/w 11111111 b 0f9e h pds01 8/16-bit ppg01 duty setting buffer register r/w 11111111 b 0f9f h pds00 8/16-bit ppg00 duty setting buffer register r/w 11111111 b 0fa0 h pps11 8/16-bit ppg11 cycle setting buffer register r/w 11111111 b 0fa1 h pps10 8/16-bit ppg10 cycle setting buffer register r/w 11111111 b 0fa2 h pds11 8/16-bit ppg11 duty setting buffer register r/w 11111111 b 0fa3 h pds10 8/16-bit ppg10 duty setting buffer register r/w 11111111 b 0fa4 h ppgs 8/16-bit ppg start register r/w 00000000 b 0fa5 h revc 8/16-bit ppg output inversion register r/w 00000000 b 0fa6 h tmrh0 16-bit reload timer timer register upper r/w 00000000 b tmrlrh0 16-bit reload timer reload register upper r/w 00000000 b 0fa7 h tmrl0 16-bit reload timer timer register lower r/w 00000000 b tmrlrl0 16-bit reload timer reload register lower r/w 00000000 b 0fa8 h pssr0 uart/sio dedicated baud ra te generator prescaler sele ct register ch. 0 r/w 00000000 b 0fa9 h brsr0 uart/sio dedicated baud rate generator baud rate setting register ch. 0 r/w 00000000 b 0faa h pssr1 uart/sio dedicated baud ra te generator prescaler sele ct register ch. 1 r/w 00000000 b 0fab h brsr1 uart/sio dedicated baud rate generator baud rate setting register ch. 1 r/w 00000000 b
mb95410h/470h series document number: 002-07475 rev. *b page 43 of 85 (continued) address register abbreviation register name r/w initial value 0fac h pssr2 uart/sio dedicated baud rate generator prescaler select register ch. 2 r/w 00000000 b 0fad h brsr2 uart/sio dedicated baud rate generator baud rate setting register ch. 2 r/w 00000000 b 0fae h ? (disabled) ? ? 0faf h aidrl a/d input disable re gister (lower) r/w 00000000 b 0fb0 h lcdcc1 lcdc control register 1 r/w 00000000 b 0fb1 h ? (disabled) ? ? 0fb2 h lcdce1 lcdc enable register 1 r/w 00111100 b 0fb3 h lcdce2 lcdc enable register 2 r/w 00000000 b 0fb4 h lcdce3 lcdc enable register 3 r/w 00000000 b 0fb5 h lcdce4 lcdc enable register 4 r/w 00000000 b 0fb6 h lcdce5 lcdc enable register 5 r/w 00000000 b 0fb7 h lcdce6 lcdc enable register 6 r/w 00000000 b 0fb8 h ? (disabled) ? ? 0fb9 h lcdcb1 lcdc blinking setting register 1 r/w 00000000 b 0fba h lcdcb2 lcdc blinking setting register 2 r/w 00000000 b 0fbb h , 0fbc h ? (disabled) ? ? 0fbd h to 0fd8 h lcdram lcdc display ram (28 bytes) r/w 00000000 b 0fd9 h to 0fe1 h ? (disabled) ? ? 0fe2 h evcr event counter control register r/w 00000000 b 0fe3 h wcdr watch counter data register r/w 00111111 b 0fe4 h crth main cr clock trimming register (upper) r/w 0xxxxxxx b 0fe5 h crtl main cr clock trimming register (lower) r/w 00xxxxxx b 0fe6 h , 0fe7 h ? (disabled) ? ? 0fe8 h sysc system configurati on register r/w 11000011 b 0fe9 h cmcr clock monitoring control register r/w xx000000 b 0fea h cmdr clock monitoring data register r 00000000 b 0feb h wdth watchdog timer selection id register (upper) r xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r xxxxxxxx b
mb95410h/470h series document number: 002-07475 rev. *b page 44 of 85 (continued) r/w access symbols initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. address register abbreviation register name r/w initial value 0fed h ? (disabled) ? ? 0fee h ilsr input level select register r/w 00000000 b 0fef h wicr interrupt pin control register r/w 01000000 b 0ff0 h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of th is bit is in determinate.
mb95410h/470h series document number: 002-07475 rev. *b page 45 of 85 16. interrupt source table interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of in- terrupt sources of the same level (occurring simultaneously) upper lower external interrupt ch. 0 irq00 fffa h fffb h l00 [1:0] high low external interrupt ch. 4 external interrupt ch. 1 irq01 fff8 h fff9 h l01 [1:0] external interrupt ch. 5 external interrupt ch. 2 irq02 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq03 fff4 h fff5 h l03 [1:0] external interrupt ch. 7 uart/sio ch. 0 irq04 fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq05 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 ffee h ffef h l06 [1:0] uart/sio ch. 2 irq07 ffec h ffed h l07 [1:0] lcd controller irq08 ffea h ffeb h l08 [1:0] 8/16-bit ppg ch. 1 (lower) irq09 ffe8 h ffe9 h l09 [1:0] uart/sio ch. 1 8/16-bit ppg ch. 1 (upper) irq10 ffe6 h ffe7 h l10 [1:0] 16-bit reload timer ch. 0 irq11 ffe4 h ffe5 h l11 [1:0] 8/16-bit ppg ch. 0 (upper) irq12 ffe2 h ffe3 h l12 [1:0] 8/16-bit ppg ch. 0 (lower) irq13 ffe0 h ffe1 h l13 [1:0] 8/16-bit composite timer ch. 1 (upper) irq14 ffde h ffdf h l14 [1:0] voltage comparator irq15 ffdc h ffdd h l15 [1:0] i 2 c irq16 ffda h ffdb h l16 [1:0] ? irq17 ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1:0] time-base timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] watch counter ? irq21 ffd0 h ffd1 h l21 [1:0] 8/16-bit composite timer ch. 1 (lower) irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0]
mb95410h/470h series document number: 002-07475 rev. *b page 46 of 85 17. electrical characteristics 17.1 absolute maximum ratings *1: these parameters are based on the condition that v ss = 0.0 v. *2: v i and v o must not exceed v cc + 0.3 v. v i must not exceed the rated voltage. however, if the maximum current to/from an input is limited by means of an external component, the i clamp rating is used instead of the v i rating. (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss ? 6v input voltage* 1 v i v ss ? 0.3 v ss ? 6v*2 output voltage* 1 v o v ss ? 0.3 v ss ? 6v*2 maximum clamp current i clamp ? 2 ? 2 ma applicable to specific pins *3 total maximum clamp current ? |i clamp | ? 20 ma applicable to specific pins *3 ?l? level maximum output current i cl ?15ma ?l? level average current i clav ?4ma average output current = operating current ? operating ratio (1 pin) ?l? level total maximum output current ? i ol ?100ma ?l? level total average output current ? i olav ?50ma total average output current = operating current ? operating ratio (total number of pins) ?h? level maximum output current i ch ? ? 15 ma ?h? level average current i chav ? ? 4ma average output current = operating current ? operating ratio (1 pin) ?h? level total maximum output current ? i oh ? ? 100 ma ?h? level total average output current ? i ohav ? ? 50 ma total average output current = operating current ? operating ratio (total number of pins) power consumption p d ?320mw operating temperature t a ? 40 ? 85 ? c storage temperature t stg ? 55 ? 150 ? c
mb95410h/470h series document number: 002-07475 rev. *b page 47 of 85 (continued) *3: applicable to the following pins: p00 to p07, p10, p11, p13 to p1 6, p20 to p22, p40 to p43, p50 to p53, p60 to p67, p90 to p 94, pa0 to pa7, pb0 to pb4, pc0 to pc7, pe0 to pe7, pf0, pf1, pg1 and pg2 (p40 to p4 3, p50 to p53, p94, pb2 to pb4 and pc4 to pc7 are only available on the mb95410h series.) ? use under recommended operating conditions. ? use with dc voltage (current). ? the hv (high voltage) signal is an input signal exceeding the v cc voltage. always connect a limiting resistor between the hv (high voltage) signal and the microcontroller before applying the hv (high voltage) signal. ? the value of the limiting resistance should be set so that when the hv (high voltage) signal is applied the input current to t he microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ? when the microcontroller drive current is low, such as in lo w power consumption modes, the hv (high voltage) input potential may pass through the protective diode to increase the potential of the v cc pin, and thus affects other devices. ? if the hv (high voltage) signal is input when the microcontrolle r power supply is off (not fixed at 0 v), since power is suppl ied from the pins, incomplete operations may be executed. ? if the hv (high voltage) input is input after power-on, since pow er is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. ? do not leave the hv (high vo ltage) input pin unconnected. ? example of a recommended circuit warning: semiconductor devices can be permane ntly damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. hv(high voltage) input (0 v to 16 v) protective diode v cc n-ch p-ch r limiting resistor input/output equivalent circuit
mb95410h/470h series document number: 002-07475 rev. *b page 48 of 85 17.2 recommended operating conditions (v ss = 0.0 v) *1: the value varies depending on the operating frequency, the machine clock and the analog guaranteed range. *2: the value is initially 2.88 v when t he low-voltage detection reset is used. * 3: use a ceramic capacitor or a capacitor with equivalent frequency characteristics. th e bypass capacitor for the v cc pin must have a capacitance larger than c s . for the connection to a smoothing capacitor c s , see the diagram below. to prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board . warning: the recommended operating conditions are required in order to ensure the norma l operation of the semiconductor device. all of the device's electrical char acteristics are warranted when the dev ice is operated within these ranges. always use semiconductor devices within thei r recommended operating condition ranges. operation outside these ranges may adversely affe ct reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represen ted on the data sheet. users considering application outside the listed conditions ar e advised to contact their representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc , av cc 2.4* 1*2 5.5* 1 v in normal operation other than on-chip debug mode 2.3 5.5 hold condition in stop mode 2.9 5.5 in normal operation on-chip debug mode 2.3 5.5 hold condition in stop mode smoothing capacitor c s 0.022 1 f *3 operating temperature t a ? 40 ? 85 ? c other than on-chip debug mode +5 ? 35 on-chip debug mode c cs dbg * since the dbg pin becomes a communication pin in on-chip debug mode, set a pull-up resistor value suiting the input/output specifications of p12/dbg. *: rst dbg / rst / c pins connection diagram
mb95410h/470h series document number: 002-07475 rev. *b page 49 of 85 17.3 dc characteristics (v cc = 5.0 v 10%, v ss = 0.0 v, t a = -40c to +85c ) (continued) parameter symbol pin name condition value unit remarks min typ max "h" level input voltage v ihi p01, p04, p10, p22, p23 *1 0.7 v cc ?v cc ? 0.3 v when cmos input level (hysteresis input) is selected v ihs p00 to p07, p10 to p17, p20 to p23, p40 to p43 *2 , p50 to p53 *2 , p60 to p67, p90 to p93, p94 *2 , pa0 to pa7, pb0, pb1, pb2 to pb4 *2 , pc0 to pc3, pc4 to pc7 *2 , pe0 to pe7, pf0, pf1, pg1, pg2 *1 0.8 v cc ?v cc ? 0.3 v hysteresis input v ihm pf2 ? 0.7 v cc ?v cc ? 0.3 v hysteresis input ?l? level input voltage v il p01, p04, p10, p22, p23 *1 v ss ? 0.3 ? 0.3 v cc v when cmos input level (hysteresis input) is selected v ils p00 to p07, p10 to p17, p20 to p23, p40 to p43 *2 , p50 to p53 *2 , p60 to p67, p90 to p93, p94 *2 , pa0 to pa7, pb0, pb1, pb2 to pb4 *2 , pc0 to pc3, pc4 to pc7 *2 , pe0 to pe7, pf0, pf1, pg1, pg2 *1 v ss ? 0.3 ? 0.2 v cc v hysteresis input v ilm pf2 ? v ss ? 0.3 ? 0.3 v cc v hysteresis input open-drain output application voltage v d p12, p22, p23, pf2 ?v ss ? 0.3 ? v ss ? 5.5 v ?h? level output voltage v oh1 output pins other than p12, p22, p23, pf2 i oh = ? 4 ma v cc ? 0.5 ? ? v
mb95410h/470h series document number: 002-07475 rev. *b page 50 of 85 (v cc = 5.0 v 10%, v ss = 0.0 v, t a = -40c to +85c) (continued) parameter symbol pin name condition value unit remarks min typ *4 max ?l? level output voltage v ol1 all output pins i ol = 4 ma ? ? 0.4 v input leak current (hi-z output leak current) i li all input pins 0.0 v < v i < v cc ? 5? ? 5a when pull-up resistance is disabled pull-up resistance r pull p10, p11, p13, p14, p17, p20, p21, p50 to p53 *2 , pg1, pg2 v i = 0 v 25 50 100 k ? when pull-up resistance is enabled input capacitance c in other than v cc and v ss f = 1 mhz ? 5 15 pf power supply current* 3 i cc v cc (external clock operation) v cc = 5.5 v f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ?14.117ma except during flash memory programming and erasing ?2039.5ma during flash memory programming and erasing i ccs v cc = 5.5 v f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ?6.6 9ma i ccl v cc = 5.5 v f cl = 32 khz f mpl = 16 khz subclock mode (divided by 2) t a = ? 25 ? c ? 60 153 a i ccls v cc = 5.5 v f cl = 32 khz f mpl = 16 khz subsleep mode (divided by 2) t a = ? 25 ? c ?984a i cct v cc = 5.5 v f cl = 32 khz watch mode main stop mode t a = ? 25 ? c ? 4.3 30 a
mb95410h/470h series document number: 002-07475 rev. *b page 51 of 85 (v cc = 5.0 v 10%, v ss = 0.0 v, t a = -40c to +85c) (continued) parameter symbol pin name condition value unit remarks min typ *4 max power supply current* 3 i ccmpll v cc (external clock operation) v cc = 5.5 v f ch = 4 mhz f mp = 10 mhz main pll mode (multiplied by 2.5) t a = ? 25 ? c ? 9.7 12.5 ma v cc = 5.5 v f ch = 6.44 mhz f mp = 16 mhz main pll mode (multiplied by 2.5) t a = ? 25 ? c ?13.920ma i ccmcr v cc v cc = 5.5 v f crh = 12.5 mhz f mp = 12.5 mhz main cr clock mode ? 11 13.2 ma i ccscr v cc = 5.5 v sub-cr clock mode (multiplied by 2.5) t a = ? 25 ? c ?112410a i ccts v cc (external clock operation) v cc = 5.5 v f ch = 32 mhz time-base timer mode t a = ? 25 ? c ?1 3ma i cch v cc = 5.5 v substop mode t a = ? 25 ? c ? 3.1 22.5 a main stop mode with one clock selected i a av cc current consumption for a/d conversion at 16 mhz ?1.54.7ma i ah current consumption for stopping a/d conversion at 16 mhz ?1 5a i v current consumption of voltage comparator at 16 mhz ?113350a
mb95410h/470h series document number: 002-07475 rev. *b page 52 of 85 (continued) (v cc = 5.0 v 10%, v ss = 0.0 v, t a = -40c to +85c) *1: the input levels of p01, p04, p10, p2 2 and p23 can be switched between ?cmos input level? and ?hysteresis input level?. the input level selection register (ilsr) is us ed to switch between the two input levels. *2: p40 to p43, p50 to p53, p94, pb2 to pb4 and pc4 to pc7 are only available on the mb95410h series. *3: ? the power supply current is determined by the external clock. when the low-voltage detection option is selected, the power- supply current will be the sum of adding the current consumption of the low-voltage detection circuit (i lvd ) to one of the value from i cc to i cch . in addition, when both the low-voltage detection option and the cr oscillator are selected, the power supply current will be the sum of adding up the current consumpt ion of the low-voltage detection circuit, the current consumption of the cr oscilla tors (i crh , i crl ) and a specified value. in on-chi p debug mode, the cr oscillator (i crh ) and the low-voltage detection circuit are always enabled, and current consumpti on therefore increases accordingly. ? see ?17.4. ac characteristics: 17.4.1. clock timing? for f ch and f cl . ? see ?17.4. ac characteristics: 17.4.2. source clock/machine clock? for f mp and f mpl . *4: v cc = 5.0 v, t a = +25c parameter symbol pin name condition value unit remarks min typ *4 max power supply current* 3 i lvd v cc current consumption of the low-voltage detection circuit ?3154a i crh current consumption of the main cr oscillator ?0.50.6ma i crl current consumption of the sub-cr oscillator oscillating at 100 khz ?2072a lcd internal division resis- tance r lcd ? between v4 and v ss ? 400 ? k ? ?40?k ? com0 to com7 output impedance r vcom com0 to com7 v1 to v4 = 4.1 v ?? 5 k ? seg00 to seg39 output impedance r vseg seg00 to seg39 ? ? 7 k ? lcd leakage current i lcdl v0 to v4, com0 to com7, seg00 to seg39 ? ? 1? ? 1a
mb95410h/470h series document number: 002-07475 rev. *b page 53 of 85 17.4 ac characteristics 17.4.1 clock timing (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = -40c to +85c) *: the external clock signal is input to x0 and the inverted external clock signal to x1. parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 16.25 mhz when the main oscillation circuit is used x0 x1: open 1 ? 12 mhz when the main external clock is used x0, x1 * 1 ? 32.5 mhz ? 3 ? 8.13 mhz main pll multiplied by 2 ? 3 ? 6.5 mhz main pll multiplied by 2.5 ? 3 ? 4.06 mhz main pll multiplied by 4 f crh ?? 12.25 12.5 12.75 mhz operating conditions: ? the main cr clock is used. ? t a = ? 10 ? c to ? 85 ? c 9.8 10 10.2 mhz 7.84 8 8.16 mhz 0.98 1 1.02 mhz ?? 12.1875 12.5 12.8125 mhz operating conditions: ? the main cr clock is used. ? t a = ? 40 ? c to ? 1 ?? c 9.75 10 10.25 mhz 7.8 8 8.2 mhz 0.975 1 1.025 mhz f cl x0a, x1a ? ? 32.768 ? khz when the sub-oscillation circuit is used ? 32.768 ? khz when the sub-external clock is used f crl ? ? 50 100 200 khz when the sub-cr clock is used clock cycle time t hcyl x0, x1 ? 61.5 ? 1000 ns when the main oscillation circuit is used x0 x1: open 83.4 ? 1000 ns when the external clock is used x0, x1 * 30.8 ? 1000 ns t lcyl x0a, x1a ? ? 30.5 ? s when the subclock is used input clock pulse width t wh1 t wl1 x0 x1: open 33.4 ? ? ns when the external clock is used, the duty ratio should range between 40% and 60%. x0, x1 * 12.4 ? ? ns t wh2 t wl2 x0a ? ? 15.2 ? s input clock rise time and fall time t cr t cf x0 x1: open ? ? 5 ns when the external clock is used x0, x1 * ? ? 5 ns cr oscillation start time t crhwk ? ? ? ? 80 s when the main cr clock is used t crlwk ? ? ? ? 10 s when the sub-cr clock is used
mb95410h/470h series document number: 002-07475 rev. *b page 54 of 85 x0, x1 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh1 t wl1 0.2 v cc t hcyl t cr t cf input waveform generated when an external clock (main clock) is used when a crystal oscillator or a ceramic oscillator is used when the external clock is used x0 x1 x0 x1 f ch f ch when the external clock is used (x1 is open) x0 x1 open f ch figure of main clock input port external connection x0a 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh2 t wl2 0.2 v cc t lcyl t cr t cf input waveform generated when an external clock (subclock) is used when a crystal oscillator or a ceramic oscillator is used when the external clock is used x0a x1a x0a x1a open f cl f cl figure of subclock input port external connection
mb95410h/470h series document number: 002-07475 rev. *b page 55 of 85 17.4.2 source clock/machine clock (v cc = 5.0 v 10%, v ss = 0.0 v, t a = -40c to +85c) * 1: this is the clock before it is divided according to the divisi on ratio set by the machine clock divide ratio select bits (syc c:div1, div0). this source clock is divided to become a machine clock according to the division ratio set by the machine clock divide r atio select bits (sycc:div1, div0). in addition, a source clo ck can be selected from the following . ? main clock divided by 2 ? pll multiplication of main clock (s elect from 2, 2.5, 4 multiplication) ? main cr clock divided by 2 ? subclock divided by 2 ? sub-cr clock divided by 2 (continued) parameter symbol pin name value unit remarks min typ max source clock cycle time* 1 t sclk ? 61.5 ? 2000 ns when the main oscillation clock is used min: f ch = 32.5 mhz, divided by 2 max: f ch = 1 mhz, divided by 2 61.5 ? 2000 ns when the main oscillation clock is used min: f ch = 8.125 mhz, multiplied by the pll multiplier of 2 max: f ch = 1 mhz, divided by 2 80 ? 1000 ns when the main cr clock is used min: f crh = 12.5 mhz max: f crh = 1 mhz ?61?s when the sub-oscillation clock is used f cl = 32.768 khz, divided by 2 ?20?s when the sub-cr clock is used f crl = 100 khz, divided by 2 source clock frequency f sp ? 0.50 ? 16.25 mhz when the main oscillation clock is used 1 ? 12.5 mhz when the main cr clock is used f spl ? 16.384 ? khz when the sub-oscillation clock is used ? 50 ? khz when the sub-cr clock is used f crl = 100 khz, divided by 2 machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when the main oscillation clock is used min: f sp = 16.25 mhz, no division max: f sp = 0.5 mhz, divided by 16 80 ? 16000 ns when the main cr clock is used min: f sp = 12.5 mhz max: f sp = 1 mhz, divided by 16 61 ? 976.5 s when the sub-oscillation clock is used min: f spl = 16.384 khz, no division max: f spl = 16.384 khz, divided by 16 20 ? 320 s when the sub-cr clock is used min: f spl = 50 khz, no division max: f spl = 50 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.25 mhz when the main oscillation clock is used 0.0625 ? 12.5 mhz when the main cr clock is used f mpl 1.024 ? 16.384 khz when the sub-oscillation clock is used 3.125 ? 50 khz when the sub-cr clock is used f crl = 100 khz
mb95410h/470h series document number: 002-07475 rev. *b page 56 of 85 (continued) *2: this is the operating clock of the microcontroller. a machine clock can be selected from the following. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 f ch (main oscillation) f crh (main cr clock) f cl (sub-oscillation) f crl (sub-cr clock) sclk (source clock) mclk (machine clock) clock mode select bits (sycc2: rcs1, rcs0) machine clock divide ratio select bits (sycc: div1, div0) division circuit 1 1/4 1/8 1/16 divided by 2 divided by 2 divided by 2 main pll 2 2.5 4 schematic diagram of the clock generation block
mb95410h/470h series document number: 002-07475 rev. *b page 57 of 85 operating voltage (v) a/d converter operation range 5.5 5.0 4.0 3.5 3.0 2.9 16 khz 3 mhz 12.5 mhz 16.25 mhz source clock frequency (f sp ) operating voltage (v) a/d converter operation range 5.5 5.0 4.0 3.5 3.0 2.4 16 khz 3 mhz 10 mhz 16.25 mhz source clock frequency (f sp /f spl ) operating voltage - operating frequency (when t a = ? 40 ? c to ? 85 ? c) with the on-chip debug function operating voltage - operating frequency (when t a = ? 40 ? c to ? 85 ? c) without the on-chip debug function
mb95410h/470h series document number: 002-07475 rev. *b page 58 of 85 17.4.3 external reset (v cc = 5.0 v 10%, v ss = 0.0 v, t a = -40c to +85c) *1: see ?17.4.2. source cl ock/machine clock? for t mclk . *2: the oscillation time of an oscillator is the time for it to reach 90% of its am plitude. the crystal oscillator has an oscill ation time of between several ms and tens of ms. the ceramic oscillator has an oscillation time of between hundreds of s and several ms. the external clock has an oscillation time of 0 ms. the cr oscill ator clock has an oscillation time of between several s and s everal ms. parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * 1 ? ns in normal operation oscillation time of the oscillator* 2 ? 100 ?s in stop mode, subclock mode, subsleep mode, watch mode, and power-on 100 ? s in time-base timer mode 0.2 v cc rst 0.2 v cc t rstl t rstl 0.2 v cc 0.2 v cc 100 s x0 internal operating clock 90% of amplitude oscillation time of oscillator oscillation stabilization wait time execute instruction internal reset rst in normal operation in stop mode, subclock mode, subsleep mode, watch mode and power-on
mb95410h/470h series document number: 002-07475 rev. *b page 59 of 85 17.4.4 power-on reset (v ss = 0.0 v, t a = -40c to +85c) note: a sudden change of power supply voltage may activate the power-on reset function. when changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mv/ms as shown below. 17.4.5 peripheral input timing (v cc = 5.0 v 10%, v ss = 0.0 v, t a = -40c to +85c) *: see ?17.4.2. source cl ock/machine clock? for t mclk . parameter symbol condition value unit remarks min max power supply rising time t r ??50ms power supply cutoff time t off ? 1 ? ms wait time until power-on parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int00 to int07, ec0, ec1, adtg 2 t mclk *? ns peripheral input ?l? pulse width t ihil 2 t mclk *? ns 0.2 v 0.2 v t off t r 2.5 v 0.2 v v cc v cc 2.3 v v ss hold condition in stop mode set the slope of rising to a value below 30 mv/ms. int00 to int07, ec0, ec1, adtg 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ilih t ihil
mb95410h/470h series document number: 002-07475 rev. *b page 60 of 85 17.4.6 uart/sio, serial i/o timing (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = -40c to +85c) *: see ?17.4.2. source cl ock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc uck0, uck1, uck2 internal clock operation output pin: c l = 80 pf ? 1 ttl 4 t mclk *? ns uck ?? uo time t slovi uck0, uck1, uck2, uo0, uo1, uo2 ? 190 ? 190 ns valid ui ? uck ? t ivshi uck0, uck1, uck2, ui0, ui1, ui2 2 t mclk *? ns uck ?? valid ui hold time t shixi uck0, uck1, uck2, ui0, ui1, ui2 2 t mclk *? ns serial clock ?h? pulse width t shsl uck0, uck1, uck2 external clock operation output pin: c l = 80 pf ? 1 ttl 4 t mclk *? ns serial clock ?l? pulse width t slsh uck0, uck1, uck2 4 t mclk *? ns uck ?? uo time t slove uck0, uck1, uck2, uo0, uo1, uo2 ? 190 ns valid ui ? uck ? t ivshe uck0, uck1, uck2, ui0, ui1, ui2 2 t mclk *? ns uck ?? valid ui hold time t shixe uck0, uck1, uck2, ui0, ui1, ui2 2 t mclk *? ns
mb95410h/470h series document number: 002-07475 rev. *b page 61 of 85 0.8 v 0.8 v 2.4 v t slovi t ivshi t shixi 2.4 v 0.8 v uck0, uck1, uck2 uo0, uo1, uo2 ui0, ui1, ui2 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc internal shift clock mode 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slove t ivshe t shixe 2.4 v 0.8 v uck0, uck1, uck2 uo0, uo1, uo2 ui0, ui1, ui2 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t slsh t shsl external shift clock mode
mb95410h/470h series document number: 002-07475 rev. *b page 62 of 85 17.4.7 low-voltage detection (v ss = 0.0 v, t a = -40c to +85c) parameter symbol value unit remarks min typ max release voltage v dl+ 2.52 2.7 2.88 v at power supply rise detection voltage v dl- 2.42 2.6 2.78 v at power supply fall hysteresis width v hys 70 100 ? mv power supply start voltage v off ??2.3v power supply end voltage v on 4.9 ? ? v power supply voltage change time (at power supply rise) t r 3000 ? ? s slope of power supply that the reset release signal generates within the rating (v dl+ ) power supply voltage change time (at power supply fall) t f 300 ? ? s slope of power supply that the reset detection signal generates within the rating (v dl- ) reset release delay time t d1 ? ? 300 s reset detection delay time t d2 ? ? 20 s v hys t d2 t d1 t r t f v cc v on v off v dl+ v dl- time time internal reset signal
mb95410h/470h series document number: 002-07475 rev. *b page 63 of 85 17.4.8 i 2 c timing (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = -40c to +85c) *1: r represents the pull-up resistor of the scl and sda lines, and c the load capacitor of the scl and sda lines. *2: the maximum t hd;dat in the standard-mode is applicable only when the ti me during which the device is holding the scl signal at ?l? (t low ) does not extend. *3: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, provided th at the condition of t su;dat 250 ns is fulfilled. (continued) parameter symbol pin name conditions value unit standard-mode fast-mode min max min max scl clock frequency f scl scl r = 1.7 k ? , c = 50 pf* 1 0 100 0 400 khz (repeat) start condition hold time sda scl t hd;sta scl, sda 4.0 ? 0.6 ? s scl clock ?l? width t low scl 4.7 ? 1.3 ? s scl clock ?h? width t high scl 4.0 ? 0.6 ? s (repeat) start condition setup time scl sda t su;sta scl, sda 4.7 ? 0.6 ? s data hold time scl sda t hd;dat scl, sda 0 3.45* 2 00.9* 3 s data setup time sda scl t su;dat scl, sda 0.25 ? 0.1 ? s stop condition setup time scl sda t su;sto scl, sda 4.0 ? 0.6 ? s bus free time between stop condition and start condition t buf scl, sda 4.7 ? 1.3 ? s sda scl t wakeup t hd;sta t su;dat f scl t hd;sta t su;sta t low t hd;dat t high t su;sto t buf
mb95410h/470h series document number: 002-07475 rev. *b page 64 of 85 (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = -40c to +85c) (continued) parameter symbol pin name conditions value* 2 unit remarks min max scl clock ?l? width t low scl r = 1.7 k ? , c = 50 pf* 1 (2 ? nm / 2)t mclk ? 20 ? ns master mode scl clock ?h? width t high scl (nm / 2)t mclk ? 20 (nm / 2)t mclk ? 20 ns master mode start condition hold time t hd;sta scl, sda ( ? 1 ? nm / 2)t mclk ? 20 ( ? 1 ? nm)t mclk ? 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto scl, sda (1 ? nm / 2)t mclk ? 20 (1 ? nm / 2)t mclk ? 20 ns master mode start condition setup time t su;sta scl, sda (1 ? nm / 2)t mclk ? 20 (1 ? nm / 2)t mclk ? 20 ns master mode bus free time between stop condition and start condition t buf scl, sda (2 nm ? 4)t mclk ? 20 ? ns data hold time t hd;dat scl, sda 3 t mclk ?? 20 ? ns master mode data setup time t su;dat scl, sda ( ? 2 ? nm / 2)t mclk ? 20 ( ? 1 ? nm / 2)t mclk ? 20 ns master mode when assuming that ?l? of scl is not extended, the minimum value is applied to first bit of continuous data. otherwise, the maximum value is applied. setup time between clearing interrupt and scl rising t su;int scl (nm / 2)t mclk ? 20 (1 ? nm / 2)t mclk ? 20 ns minimum value is applied to interrupt at 9th scl . maximum value is applied to interrupt at 8th scl . scl clock ?l? width t low scl 4 t mclk ? 20 ? ns at reception scl clock ?h? width t high scl 4 t mclk ? 20 ? ns at reception
mb95410h/470h series document number: 002-07475 rev. *b page 65 of 85 (continued) (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = -40c to +85c) *1: r represents the pull-up resistor of the scl and sda lines, and c the load capacitor of the scl and sda lines. *2: ? see ?17.4.2. source clock/machine clock? for t mclk . ? m represents the cs4 bit and cs3 bit (bit4 and bit3) in the i 2 c clock control register (iccr0). ? n represents the cs2 bit to cs0 bit (bit2 to bit0) in the i 2 c clock control register (iccr0). ? the actual timing of i 2 c is determined by the values of m and n set by the machine clock (t mclk ) and the cs4 to cs0 bits in the iccr0 register. ? standard-mode: m and n can be set to values in the following range: 0.9 mhz < t mclk (machine clock) < 16.25 mhz. the usable frequencies of the machine clock are dete rmined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 mhz < t mclk 1 mhz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 mhz < t mclk 2 mhz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 mhz < t mclk 4 mhz (m, n) = (1, 98), (5, 22), (6, 22), (7, 22) : 0.9 mhz < t mclk 10 mhz (m, n) = (8, 22) : 0.9 mhz < t mclk 16.25 mhz ? fast-mode: m and n can be set to values in the following range: 3.3 mhz < t mclk (machine clock) < 16.25 mhz. the usable frequencies of the machine clock are dete rmined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 mhz < t mclk 4 mhz (m, n) = (1, 22), (5, 4) : 3.3 mhz < t mclk 8 mhz (m, n) = (1, 38), (6, 4), (7, 4), (8, 4) : 3.3 mhz < t mclk 10 mhz (m, n) = (5, 8) : 3.3 mhz < t mclk 16.25 mhz parameter symbol pin name conditions value* 2 unit remarks min max start condition detection t hd;sta scl, sda r = 1.7 k ? , c = 50 pf* 1 2 t mclk ? 20 ? ns not detected when 1 t mclk is used at reception stop condition detection t su;sto scl, sda 2 t mclk ? 20 ? ns not detected when 1 t mclk is used at reception restart condition detection condition t su;sta scl, sda 2 t mclk ? 20 ? ns not detected when 1 t mclk is used at reception bus free time t buf scl, sda 2 t mclk ? 20 ? ns at reception data hold time t hd;dat scl, sda 2 t mclk ? 20 ? ns at slave transmission mode data setup time t su;dat scl, sda t low ? 3 t mclk ? 20 ?ns at slave transmission mode data hold time t hd;dat scl, sda 0 ? ns at reception data setup time t su;dat scl, sda t mclk ? 20 ? ns at reception sda scl (at wakeup function) t wakeup scl, sda oscillation stabilization wait time ? 2 t mclk ? 20 ?ns
mb95410h/470h series document number: 002-07475 rev. *b page 66 of 85 17.4.9 voltage comparator timing (av cc = 4.0 v to 5.5 v, av ss = 0.0 v, t a = -40c to +85c) parameter pin name value unit remarks min typ max voltage range cmpp, cmpn 0 ? av cc ? 1.3 v offset voltage cmpp, cmpn ? 10 ? ? 10 mv delay time cmpo ? 650 1210 ns 5 mv overdrive ? 140 420 ns 50 mv overdrive power down delay cmpo ? ? 1210 ns power down recovery pd: 1 ? 0 0??ns power down effective pd: 0 ? 1 output: ?h? level power up stabilization time cmpo ? ? 1210 ns output stabilization time at power up bandgap reference voltage ? 1.17 1.22 1.27 v
mb95410h/470h series document number: 002-07475 rev. *b page 67 of 85 17.5 a/d converter 17.5.1 a/d converter electrical characteristics (av cc = v cc = 4.0 v to 5.5 v, av ss = v ss = 0.0 v, t a = -40c to +85c) parameter symbol value unit remarks min typ max resolution ? ??10bit total error ? 3? ? 3lsb linearity error ? 2.5 ? ? 2.5 lsb differential linear error ? 1.9 ? ? 1.9 lsb zero transition voltage v ot av ss ? 1.5 lsb av ss ? 0.5 lsb av ss ? 2.5 lsb v full-scale transition voltage v fst av cc ? 4.5 lsb av cc ? 2 lsb av cc ? 0.5 lsb v compare time ? 0.9 ? 16500 s 4.5 v ?? v cc ?? 5.5 v 1.8 ? 16500 s 4.0 v ?? v cc < ? 4.5 v sampling time ? 0.6 ? s 4.5 v ?? v cc ??? 5.5 v, with external impedance < 5.4 k ? 1.2 ? s 4.0 v ??? v cc < ? 4.5 v, with external impedance < 2.4 k ? analog input current i ain ? 0.3 ? ? 0.3 a analog input voltage v ain av ss ?av cc v
mb95410h/470h series document number: 002-07475 rev. *b page 68 of 85 17.5.2 notes on using the a/d converter external impedance of analog input and its sampling time the a/d converter has a sample and hold circuit. if the external impedance is too high to keep sufficient sampling time, the an alog voltage charged to the capacitor of the internal sample and hol d circuit is insufficient, adversely affecting a/d conversion pr ecision. therefore, to satisfy the a/d conversion precision standard, consid ering the relationship between the external impedance and minimum sampling time, either adjust the register value and oper ating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. in addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 f to the analog input pin. a/d conversion error as |v cc ? v ss | decreases, the a/d conversion error increases proportionately. note: the values are reference values. 4.5 v v cc 5.5 v 4.0 v v cc < 4.5 v 1.95 k (max) 8.98 k (max) 17 pf (max) v cc r c 17 pf (max) comparator analog input during sampling: on r c analog input equivalent circuit [external impedance = 0 k to 100 k ] external impedance [k ] external impedance [k ] minimum sampling time [ s] minimum sampling time [ s] [external impedance = 0 k to 20 k ] 100 90 80 70 60 50 40 30 20 10 0 20 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 101214 1 0 234 (v cc 4.5 v) (v cc 4.0 v) (v cc 4.5 v) (v cc 4.0 v) relationship between external impe dance and minimum sampling time
mb95410h/470h series document number: 002-07475 rev. *b page 69 of 85 17.5.3 definitions of a/d converter terms resolution it indicates the level of analog variation t hat can be distinguished by the a/d converter. when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. linearity error (unit: lsb) it indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (?00 0000 0000? ??? ?00 0000 0001?) of a device to the full-scale transition point (?11 1111 1111? ??? ?11 1111 1110?) of the same device. differential linear error (unit: lsb) it indicates how much the input voltage required to chang e the output code by 1 lsb dev iates from an ideal value. total error (unit: lsb) it indicates the difference between an actual value and a theoreti cal value. the error can be caused by a zero transition error , a full-scale transition errors, a linearity error, a quantum error, or noise. (continued) v fst ideal i/o characteristics 001 h 002 h 003 h 004 h 3fd h 3fe h 3ff h digital output digital output 2 lsb v ot 1 lsb 0.5 lsb total error analog input analog input 001 h 002 h 003 h 004 h 3fd h 3fe h 3ff h actual conversion characteristic ideal characteristic actual conversion characteristic n v nt : a/d converter digital output value : voltage at which the digital output transits from (n - 1) h to n h {1 lsb (n-1) + 0.5 lsb} v nt total error of digital output n v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb [lsb] = v cc - v ss 1024 (v) 1 lsb = v ss v cc v ss v cc
mb95410h/470h series document number: 002-07475 rev. *b page 70 of 85 (continued) zero transition error linearity error full-scale transition error 001 h 002 h 003 h 004 h 3fd h 3fe h 3ff h digital output differential linear error of digital output n v (n+1)t - v nt 1 lsb - 1 = linearity error of digital output n v nt - {1 lsb n + v ot } 1 lsb = digital output analog input 001 h 002 h 3fc h 3fd h 003 h 3fe h 3ff h 004 h actual conversion characteristic actual conversion characteristic v ot (measurement value) actual conversion characteristic actual conversion characteristic v fst (measurement value) v ss v cc v ss v cc v ss v cc v ss v cc analog input digital output analog input ideal characteristic {1 lsb n + v ot } actual conversion characteristic ideal characteristic actual conversion characteristic v ot (measurement value) v fst (measurement value) v nt differential linearity error (n-2) h (n-1) h n h (n+1) h digital output analog input actual conversion characteristic ideal characteristic v nt actual conversion characteristic v (n+1)t n v nt : a/d converter digital output value : voltage at which the digital output transits from (n - 1) h to n h v ot (ideal value) = v ss + 0.5 lsb [v] v fst (ideal value) = v cc - 2 lsb [v] ideal characteristic
mb95410h/470h series document number: 002-07475 rev. *b page 71 of 85 17.6 flash memory program/erase characteristics *1: t a = +25c, v cc = 5.0 v, 100000 cycles *2: t a = +85c, v cc = 3.0 v, 100000 cycles *3: this value is converted from the result of a technology relia bility assessment. (the value is converted from the result of a high temperature accelerated test using the arrhenius equation with the average temperature being +85c). parameter value unit remarks min typ max sector erase time (2 kbyte sector) ?0.2* 1 0.5* 2 s the time of writing 00 h prior to erasure is excluded. sector erase time (16 kbyte sector) ?0.5* 1 7.5* 2 s the time of writing 00 h prior to erasure is excluded. byte writing time ? 21 6100* 2 s system-level overhead is excluded. program/erase cycle 100000 ? ? cycle power supply voltage at program/erase 3.0 ? 5.5 v flash memory data retention time 20* 3 ? ? year average t a = ? 85 ? c
mb95410h/470h series document number: 002-07475 rev. *b page 72 of 85 18. sample characteristics power supply current temperature characteristics (continued) 0 5 10 15 20 234567 i cc [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz i cc - v cc t a = +25c, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) main clock mode with the external clock operating 0 5 10 15 20 i cc [ma] ? 50 0 + 50 + 100 + 150 t a [ c] f mp = 16 mhz f mp = 10 mhz 0 5 10 15 20 234567 i ccs [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 5 10 15 20 i ccs [ma] ? 50 0 + 50 + 100 + 150 t a [ c] f mp = 16 mhz f mp = 10 mhz 0 25 50 75 100 234567 i ccl [ a] v cc [v] 0 25 50 75 100 i ccl [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i cc - t a v cc = 5.5 v, f mp = 10, 16 mhz (divided by 2) main clock mode with the external clock operating i ccs - v cc t a = +25c, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccs - t a v cc = 5.5 v, f mp = 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccl - v cc t a = +25c, f mpl = 16 khz (divided by 2) subclock mode with the external clock operating i ccl - t a v cc = 5.5 v, f mpl = 16 khz (divided by 2) subclock mode with the external clock operating
mb95410h/470h series document number: 002-07475 rev. *b page 73 of 85 (continued) 0 25 50 75 100 i cct [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i cct - t a v cc = 5.5 v, f mpl = 16 khz (divided by 2) watch mode with the external clock operating 0 25 50 75 100 i ccls [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i ccls - t a v cc = 5.5 v, f mpl = 16 khz (divided by 2) subsleep mode with the external clock operating 0 25 50 75 100 234567 i ccls [ a] v cc [v] 0 25 50 75 100 234567 i cct [ a] v cc [v] 0.0 0.5 1.0 1.5 2.0 234567 i ccts [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0.0 0.5 1.0 1.5 2.0 i ccts [ma] ? 50 0 + 50 + 100 + 150 t a [ c] f mp = 16 mhz f mp = 10 mhz i ccls - v cc t a = +25c, f mpl = 16 khz (divided by 2) subsleep mode with the external clock operating i cct - v cc t a = +25c, f mpl = 16 khz (divided by 2) watch mode with the external clock operating i ccts - v cc t a = +25c, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating i ccts - t a v cc = 5.5 v, f mp = 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating
mb95410h/470h series document number: 002-07475 rev. *b page 74 of 85 (continued) 0 5 10 15 20 i cch [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i cch - t a v cc = 5.5 v, f mpl = (stop) substop mode with the external clock stopping 0 5 10 15 20 234567 i cch [ a] v cc [v] 0 5 10 15 20 234567 i ccmcr [ma] v cc [v] f mp = 12.5 mhz f mp = 10 mhz f mp = 8 mhz f mp = 1 mhz 0 5 10 15 20 i ccmcr [ma] f mp = 12.5 mhz f mp = 10 mhz f mp = 8 mhz f mp = 1 mhz ? 50 0 + 50 + 100 + 150 t a [ c] 0 20 40 60 80 160 140 120 100 234567 i ccscr [ a] v cc [v] 0 20 40 60 80 160 140 120 100 i ccscr [ a] ? 50 0 + 50 + 100 + 150 t a [ c] i cch - v cc t a = +25c, f mpl = (stop) substop mode with the external clock stopping i ccmcr - v cc t a = +25c, f mp = 1, 8, 10, 12.5 mhz (no division) main clock mode with the main cr clock operating i ccmcr - t a v cc = 5.5 v, f mp = 1, 8, 10, 12.5 mhz (no division) main clock mode with the main cr clock operating i ccscr - v cc t a = +25c, f mpl = 50 khz (divided by 2) subclock mode with the sub-cr clock operating i ccscr - t a v cc = 5.5 v, f mpl = 50 khz (divided by 2) subclock mode with the sub-cr clock operating
mb95410h/470h series document number: 002-07475 rev. *b page 75 of 85 input voltage characteristics 0 1 2 4 3 5 2345 7 6 v ihi /v ili [v] v cc [v] v ihi v ili 0 1 2 4 3 5 2345 7 6 v ihs /v ils [v] v cc [v] v ihs v ils v ihi - v cc and v ili - v cc t a = +25c v ihs - v cc and v ils - v cc t a = +25c 0 1 2 4 3 5 2345 7 6 v ihm /v ilm [v] v cc [v] v ihm v ilm v ihm - v cc and v ilm - v cc t a = +25c
mb95410h/470h series document number: 002-07475 rev. *b page 76 of 85 output voltage characteristics 024 i ol [ma] 6810 1.0 0.8 0.6 v ol1 [v] 0.4 0.2 0.0 v cc = 2.4 v v cc = 2.7 v v cc = 3.5 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v ol1 - i ol t a = +25c 0 ? 2 ? 4 i oh [ma] ? 6 ? 8 ? 10 1.0 0.8 0.6 v cc ? v oh1 [v] 0.4 0.2 0.0 v cc = 2.4 v v cc = 2.7 v v cc = 3.5 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v (v cc - v oh1 ) - i oh t a = +25c
mb95410h/470h series document number: 002-07475 rev. *b page 77 of 85 pull-up characteristics 0 50 150 100 250 200 23456 r pull [k ] v cc [v] r pull ? v cc t a ? ? 25 ? c
mb95410h/470h series document number: 002-07475 rev. *b page 78 of 85 19. mask options no. part number mb95f414h mb95f416h mb95f418h mb95f474h mb95f476h mb95f478h mb95f414k mb95f416k mb95f418k mb95f474k mb95f476k mb95f478k selectable/fixed fixed 1 low-voltage detection reset without low-voltage detection reset with low-voltage detection reset 2 reset with dedicated reset input without dedicated reset input
mb95410h/470h series document number: 002-07475 rev. *b page 79 of 85 20. ordering information part number package mb95f414hpmc-g-sne2 mb95f414kpmc-g-sne2 mb95f416hpmc-g-sne2 mb95f416kpmc-g-sne2 mb95f418hpmc-g-sne2 mb95f418kpmc-g-sne2 80-pin plastic lqfp (fpt-80p-m37) mb95f474hpmc1-g-sne2 mb95f474kpmc1-g-sne2 mb95f476hpmc1-g-sne2 mb95f476kpmc1-g-sne2 mb95f478hpmc1-g-sne2 mb95f478kpmc1-g-sne2 64-pin plastic lqfp (fpt-64p-m38) mb95f474hpmc2-g-sne2 mb95f474kpmc2-g-sne2 MB95F476HPMC2-G-SNE2 mb95f476kpmc2-g-sne2 mb95f478hpmc2-g-sne2 mb95f478kpmc2-g-sne2 64-pin plastic lqfp (fpt-64p-m39)
mb95410h/470h series document number: 002-07475 rev. *b page 80 of 85 21. package dimension (continued) 80-pin plastic lqfp lead pitch 0.50 mm package width package length 12.00 mm 12.00 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 1.70 mm max weight 0.47 g 80-pin plastic lqfp (fpt-80p-m37) (fpt-80p-m37) 2009-2010 fujitsu semiconductor limited f80037s-c-1-2 120 40 21 60 41 80 61 index *12.00 0.10(.472 .004)sq 14.00 0.20(.551 .008)sq 0.50(.020) 0.22 0.05 (.009 .002) m 0.08(.003) 0.145 0.055 (.006 .002) 0.08(.003) "a" (stand off) details of "a" part (.004 .002) 0.10 0.05 (.024 .006) 0.60 0.15 (.020 .008) 0.25(.010) 0.50 0.20 (mounting height) .059 ? .004 +.008 ? 0.10 +0.20 1.50 0~8 c dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
mb95410h/470h series document number: 002-07475 rev. *b page 81 of 85 (continued) 64-pin plastic lqfp lead pitch 0.50 mm package width package length 10.00 mm 10.00 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 1.70 mm max weight 0.32 g 64-pin plastic lqfp (fpt-64p-m38) (fpt-64p-m38) "a" 0.08(.003) (.006 .002) 0.145 0.055 0.08(.003) m (.009 .002) 0.22 0.05 0.50(.020) 12.00 0.20(.472 .008)sq *10.00 0.10(.394 .004)sq index 49 64 33 48 17 32 16 1 2010 fujitsu semiconductor limited f64038s-c-1-2 (stand off) details of "a" part (.004 .004) 0.10 0.10 (.024 .006) 0.60 0.15 (.020 .008) 0.25(.010) c 0.50 0.20 (mounting height) .059 ? .004 +.008 ? 0.10 +0.20 1.50 0~8 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
mb95410h/470h series document number: 002-07475 rev. *b page 82 of 85 (continued) 64-pin plastic lqfp lead pitch 0.65 mm package width package length 12.00 mm 12.00 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max weight 0.47 g 64-pin plastic lqfp (fpt-64p-m39) (fpt-64p-m39) "a" 0.10(.004) (.006 .002) 0.145 0.055 0.13(.005) m (.013 .002) 0.32 0.05 0.65(.026) 14.00 0.20(.551 .008)sq 12.00 0.10(.472 .004)sq index 49 64 33 48 17 32 16 1 2010-2011 fujitsu semiconductor limited hmbf64-39sc-2-2 details of "a" part (.004 .004) 0.10 0.10 (.024 .006) 0.60 0.15 0.25(.010)bsc c .059 ? .004 +.008 ? 0.10 +0.20 1.50 0~8? (.020 .008) 0.50 0.20 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) pins width and pins thickness include plating thickness.
mb95410h/470h series document number: 002-07475 rev. *b page 83 of 85 22. major changes spansion publication number: ds702-00004-1v0-e note: please see ?document history? about later revised information. page section details 1? changed the family name. f 2 mc-8fx ? new 8fx 49 to 51 electrical characteristics 3. dc characteristics changed the values of the following power supply current param- eters: i cc , i ccs , i ccl , i ccls , i cct , i ccmpll , i ccmcr , i ccscr , i ccts , i cch , i a , i v , i lvd . 52 electrical characteristics 4. ac characteristics (1) clock timing changed the values of the clock frequency (f crh ). 64 electrical characteristics 4. ac characteristics (8) i 2 c timing changed the settings related to the machine clock shown in *2. 71 to 76 sample characteristics added ?sample characteristics?.
mb95410h/470h series document number: 002-07475 rev. *b page 84 of 85 document history document title: mb95410h/470h series new 8fx 8-bit microcontrollers document number: 002-07475 revision ecn orig. of change submission date description of change ** ? akih 05/17/2011 migrated to cypress and assigned document number 002-07475. no change to document contents or format *a 5198834 akih 04/04/2016 updated to cypress format. *b 5861647 ysat 08/24/2017 adapted new cypress logo
document number: 002-07475 rev. *b revised august 24, 2017 page 85 of 85 mb95410h/470h series ? cypress semiconductor corporation 2010-2017. this document is the property of cypress semiconductor corporation and its subsi diaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you under its copyright rights in the software, a personal, non-exclusive, nontransferable license (without the r ight to sublicense) (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units. cypress also gran ts you a personal, non-exclusive, nontransferable, license (without the right to sublicense) under those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. any oth er use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desi gn, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or au thorized for use as critical components in systems designed or intended for the operation of w eapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants ), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. cypress is not liab le, in whole or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and h old cypress harmless from and agains t all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any unintended uses of cypress pro ducts. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete li st of cypress trademarks, visit cypress.com. other names and bra nds may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support

▲Up To Search▲

Price & Availability of MB95F476HPMC2-G-SNE2

	To Download MB95F476HPMC2-G-SNE2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .